x86-64.net

Instruction

CVTTSD2SI

Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero.

Extensions
Forms
4 (4 Legacy)
Data
Intel XED v2026.08.23

CVTTSD2SI converts the low double of an XMM register or of eight bytes of memory to a signed integer in a 32-bit or 64-bit general-purpose register, truncating toward zero whatever MXCSR.RC says. It is the instruction behind C’s casts from double: GCC 14 and Clang 23 at -O2 compile (int)x to cvttsd2si eax, xmm0 and (long)x to cvttsd2si rax, xmm0. CVTTSS2SI does the same for singles, and its page covers the integer indefinite, the unsigned conversions and the x87 history; this one adds what is particular to doubles. CVTSD2SI rounds as MXCSR says instead.

Cases recorded on Zen 5

  • 0.5 truncated to 0 and set PE: any fraction lost counts as inexact.
  • -2^32 does not fit 32 bits, so the 32-bit form gave the integer indefinite, 80000000h, and set IE. A double has room for every 32-bit integer, so out-of-range inputs to the 32-bit form are those that truncate below -2^31 or to 2^31 and above, besides NaNs and infinities.

Its other uses in compiled code

Truncation is the first step of other operations:

  • Testing whether a double holds an integer, x == (int)x: GCC converts with CVTTSD2SI, back with CVTSI2SD, and compares with UCOMISD; Clang uses the packed CVTTPD2DQ and CVTDQ2PD and compares with CMPEQSD.
  • (int)floor(x) for the baseline, which has no rounding instruction: GCC inlines floor by truncating with the 64-bit form, converting back and subtracting 1 where that went up, then converts with CVTTSD2SI; Clang calls floor. With SSE4.1 both use ROUNDSD and then CVTTSD2SI.
  • (unsigned)x uses the 64-bit form and keeps the low half, which is right for every value from 0 to 4,294,967,295.

AMD’s Zen 5 guide lists CVTTSD2SI as two macro-ops, and gives its EVEX form a latency of four cycles. VCVTTSD2USI converts to an unsigned integer, and AVX10.2’s VCVTTSD2SIS saturates instead of giving the indefinite value.

Forms

Every encoding of CVTTSD2SI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
CVTTSD2SI r32, m64 CVTTSD2SI_GPR32d_MEMsdF2 0F 2C /rSSE2
CVTTSD2SI r32, xmm CVTTSD2SI_GPR32d_XMMsdF2 0F 2C /rSSE2
CVTTSD2SI r64, m64 CVTTSD2SI_GPR64q_MEMsdF2 REX.W 0F 2C /rSSE2
CVTTSD2SI r64, xmm CVTTSD2SI_GPR64q_XMMsdF2 REX.W 0F 2C /rSSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low double of xmm2 is converted, and the integer goes to r32.
CVTTSD2SI: the low element to r32r32 receives the conversion of double 0 of xmm2: r0.01xmm2ar0r32

r32 receives the conversion of double 0 of xmm2: r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src2.f64[0]
dest.write(cvtt_int(a, dest.bits))  # r32: bits 63:32 cleared

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
CVTTSD2SI r32, xmm/m64 CVTTSD2SI r64, xmm/m64
r32/64explicitwrite
xmm/m64explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms
follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTTSD2SI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvttsd_si32 int _mm_cvttsd_si32(__m128d __a)

CVTTSD2SI r32, xmm Legacy -msse2

_mm_cvttsd_si64 long long _mm_cvttsd_si64(__m128d __a)

CVTTSD2SI r64, xmm Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SSE2

SSE2
CPUID.01H:EDX[26] SSE2

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-253 (CVTTSD2SI)
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  6. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.