CVTTSS2SI instruction (SSE)

CVTTSS2SI converts the low single of an XMM register or memory to a signed integer in a general-purpose register, rounding toward zero whatever MXCSR says. The extra T stands for that truncation: CVTSS2SI rounds as MXCSR.RC says instead. C’s casts truncate, so GCC 14 and Clang 23 at -O2 compile (int)x to cvttss2si eax, xmm0 and (long)x to the REX.W form with RAX; lrintf(x), which rounds by the current mode, becomes CVTSS2SI once -fno-math-errno lets the compilers inline it.

The x87 FIST rounds as its control word says, so x87 code changes the rounding mode around every cast. Intel’s optimization guide counts avoiding that as reason enough to use the SSE conversions wherever C truncates (Sections 3.9.3.1 and 7.5.2); SSE3’s FISTTP later gave the x87 a truncating store too.

Out of range

A NaN, an infinity or a value whose integer part does not fit becomes the integer indefinite: 80000000H for a 32-bit destination, 8000000000000000H for a 64-bit one, the most negative integer in both. The conversion also sets IE, or raises #XM if that is unmasked. So 3e9 converts to -2147483648, a large positive input giving a negative result; C leaves the conversion of an out-of-range value undefined, and languages that define it, as Rust saturates, need extra instructions around CVTTSS2SI or AVX10.2’s VCVTTSS2SIS (see VCVTTPS2DQS).

Unsigned results

No SSE form converts to an unsigned integer. For (unsigned)x, both compilers convert to 64 bits with CVTTSS2SI and keep the low half, which covers 0 to 4,294,967,295. For a 64-bit unsigned result, values of 2^63 and up need a second conversion of x - 2^63: GCC branches on a compare with 2^63, Clang computes both and combines them without a branch. With AVX-512 both use VCVTTSS2USI, which gives FFFFFFFFH or all ones in 64 bits for a value out of its range. CVTTSD2SI is the version for doubles, and CVTTPS2DQ the packed one that vectorized loops use.

Forms

Every encoding of CVTTSS2SI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CVTTSS2SI r32, m32` CVTTSS2SI_GPR32d_MEMss	`F3 0F 2C /r`	SSE
`CVTTSS2SI r32, xmm` CVTTSS2SI_GPR32d_XMMss	`F3 0F 2C /r`	SSE
`CVTTSS2SI r64, m32` CVTTSS2SI_GPR64q_MEMss	`F3 REX.W 0F 2C /r`	SSE
`CVTTSS2SI r64, xmm` CVTTSS2SI_GPR64q_XMMss	`F3 REX.W 0F 2C /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low single of xmm2 is converted, and the integer goes to r32.

r32 receives the conversion of single 0 of xmm2: r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src2.f32[0]
dest.write(cvtt_int(a, dest.bits))  # r32: bits 63:32 cleared

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CVTTSS2SI r32, xmm/m32` `CVTTSS2SI r64, xmm/m32`
`r32/64`	explicit	write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTTSS2SI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtt_ss2si` `int _mm_cvtt_ss2si(__m128 __a)`	`CVTTSS2SI r32, xmm` Legacy -msse
`_mm_cvttss_si32` `int _mm_cvttss_si32(__m128 __a)`	`CVTTSS2SI r32, xmm` Legacy -msse
`_mm_cvttss_si64` `long long _mm_cvttss_si64(__m128 __a)`	`CVTTSS2SI r64, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Out of range#

Unsigned results#