CWD instruction (General-purpose)

CWD fills DX with copies of the sign bit of AX, so that DX:AX holds the value of AX as a signed 32-bit number: the dividend that a 16-bit IDIV divides. It is opcode 99 with a 66 prefix, two bytes; AT&T syntax calls it cwtd. It reads only AX, writes only DX and changes no flag. As a 16-bit write it keeps bits 63:16 of RDX: in Zen 5’s 8 recorded cases, AX = 8000H made DX FFFFH and AX = 7FFFH made it 0000H, with the rest of RDX as it was.

The word in two registers

CWD and CWDE both widen AX to 32 bits, but put the result in different places. CWDE extends in place, into EAX; CWD writes the upper half into another register, the pair DX:AX that 16-bit MUL and IDIV use for their wide operand. The same split survives at the larger sizes: CDQ and CQO fill EDX and RDX for 32- and 64-bit division, while CDQE widens EAX in place.

In compiled code

C converts short and signed char operands to int before dividing, and GCC 14 at -O2 always divides them with CDQ and a 32-bit IDIV, first widening both with MOVSX. Clang 23 does the same for short, but for signed char, where the quotient of two bytes always fits in 16 bits, it emits mov eax, edi, cwd and idiv si, a 16-bit division, trusting the caller to have extended the arguments.

Cost

Intel’s optimization manual groups CWD with CDQ: denser than the MOV and shift it replaces but no cheaper in micro-ops, and replaceable by xor dx, dx when AX is known not to be negative (Section 3.5.1.1). That XOR is also what the unsigned DIV needs, where CWD would be wrong for any AX of 8000H and above.

Forms

Every encoding of CWD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CWD` CWD	`66 99`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`CWD`
Sandy Bridge	2 / 1p015
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	2 / 0.5p0156
Alder Lake, Sapphire Rapids	2 / 0.5p0 p1 p5 p6 p11
Lunar Lake	2 / 0.33p012345
Bonnell	4 / 2p01
Silvermont	1 / 0.5IEC0 IEC1
Piledriver	1 / 1EX0 EX1
Zen, Zen 2, Zen 3, Zen 4	1 / 0.25ALU0 ALU1 ALU2 ALU3
Jaguar	1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dx = -1 if msb(ax) else 0        # every bit a copy of AX's sign (-1: all
                                 # ones); bits 63:16 of RDX stay

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CWD`
`DX`	implicit	write
`AX`	implicit	read

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

The word in two registers#

In compiled code#

Cost#