CWDE instruction (General-purpose)

CWDE sign-extends AX into EAX: bits 31:16 become copies of bit 15. It is opcode 98 alone, one byte, and AT&T syntax calls it cwtl. Being a 32-bit write in 64-bit mode, it also clears bits 63:32 of RAX, so the result is the value of AX as a signed 32-bit number, zero-extended to 64 bits. Zen 5 turned AX = 8000H under random upper bits into RAX = 00000000FFFF8000H and 7FFFH into 0000000000007FFFH. It changes no flag. CQO has the table of the whole family.

The shortest MOVSX

movsx eax, ax (0F BF C0) computes the same result in three bytes, and MOVSX can take any register or memory. GCC 14 and Clang 23 at -O2 pick CWDE when the short is already in AX and the result belongs in EAX, which means the value a call returned: int f(void) { return gs(); }, with gs returning short, compiles to call gs and cwde with both. For a short argument, which arrives in EDI, GCC emits movsx eax, di, and Clang trusts the caller to have extended it already, as the MOVSX page explains.

Not to 64 bits

For a long result, the same call ends with movsx rax, ax: CWDE stops at bit 31, and the zeros it leaves in bits 63:32 would turn a negative short into a large positive long. A REX.W prefix makes the opcode CDQE, which extends from bit 31 instead of bit 15, so two instructions, CWDE and CDQE, would be needed where the one MOVSX does.

Names

Intel and AMD call it CWDE, extending a word into the doubleword in EAX, to keep it apart from CWD, which extends AX into DX instead. In 16-bit code the bytes are swapped around: there 98 alone is CBW and 66 98 is CWDE.

Forms

Every encoding of CWDE that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CWDE` CWDE	`98`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`CWDE`
Sandy Bridge	1 / 0.33p015
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	1 / 0.25p0156
Alder Lake, Sapphire Rapids	1 / 0.5p15
Lunar Lake	1 / 0.5V2 V3
Bonnell	4 / 2p01
Silvermont	1 / 0.5IEC0 IEC1
Piledriver	1 / 1EX0 EX1
Zen, Zen 2, Zen 3, Zen 4	1 / 0.25ALU0 ALU1 ALU2 ALU3
Jaguar	1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

eax = sext(ax, 16)               # bits 63:32 of RAX cleared

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CWDE`
`EAX`	implicit	write
`AX`	implicit	read

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I386` General-purpose	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

The shortest MOVSX#

Not to 64 bits#

Names#