DAA instruction (General-purpose)

DAA turns the binary sum of two packed BCD bytes in AL, each holding two decimal digits, into the packed BCD sum. An ADD of 58h and 47h leaves 9Fh: the low digit is above 9, so DAA adds 6 (A5h), and AL was above 99h, so it adds 60h, leaving 05h with CF set, which is 105 written in decimal. The two tests use AL and CF as they were before DAA: the low digit is corrected when it exceeds 9 or AF reports a carry out of it, the high one when AL exceeded 99h or CF reports a carry out of the byte. AF and CF then say which corrections were made, SF, ZF and PF follow the result, and OF is undefined.

A longer number is added a byte at a time from the low end, ADD then ADC for each further byte, with a DAA after each, CF carrying the decimal carry to the next byte. DAS is the same for a subtraction, AAA the unpacked form with one digit per byte.

The manuals’ wording

AMD’s Volume 3 says that AF and CF are left alone where no correction is made, and Intel’s pseudocode clears them; it comes to the same, since a set AF or CF forces its correction. Both give OF as undefined.

Not in 64-bit mode

Opcode 27 raises #UD in 64-bit mode, and the fixture has no case for DAA for that reason: the probe runs there and lists the form as not run. GNU as 2.44 and Clang 23 refuse daa in 64-bit code, and GCC 14 and Clang 23 have no intrinsic for it. Packed BCD of up to 18 digits converts to and from binary in one instruction each with x87’s FBLD and FBSTP, which 64-bit mode kept. AMD’s Zen 5 guide lists DAA as microcoded, without a latency.

Forms

Every encoding of DAA that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`DAA` not in 64-bit mode DAA	`27`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = al
c = cf
r = a
if (a & 0xF) > 9 or af:          # the low digit overflowed
    r += 6
    af = 1
else:
    af = 0
if a > 0x99 or c:                # the high digit, by AL and CF as they
    r += 0x60                    # were before the instruction
    cf = 1
else:
    cf = 0
al = r
sf = r >> 7 & 1
zf = (r & 0xFF) == 0
pf = parity(r)
of = UNDEFINED

Not run on a processor: the instruction does not exist in 64-bit mode, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`DAA` not in 64-bit mode
`AL`	implicit	read, write
`RFLAGS`	implicit	read, write

Flags

T tested, M modified, U undefined; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
U	M	M	TM	M	TM

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

The manuals’ wording#

Not in 64-bit mode#