DAS instruction (General-purpose)

DAS is DAA for subtraction: after a SUB of one packed BCD byte from another, it turns the binary difference in AL into the packed BCD difference. A SUB of 47h from 52h leaves 0Bh with AF set; the low digit is above 9, so DAS subtracts 6, leaving 05h, and AL was not above 99h and CF was clear, so the high digit stays. Subtracting 6 corrects a low digit that is above 9 or borrowed (AF set); subtracting 60h corrects the high digit when AL was above 99h or CF was set, both tests using AL and CF as they were before DAS.

Where CF comes from

CF reports a decimal borrow out of the byte. The 60h step sets it, and so does the 6 step when it borrows from AL itself, which happens when AF is set and AL is 0 to 5: AL = 03h with AF set and CF clear becomes FDh with CF set, as Intel’s pseudocode and AMD’s Volume 3 both give it. Otherwise CF is clear. AF is set when the 6 step ran, SF, ZF and PF follow the result, and OF is undefined. As with DAA, a longer number is subtracted a byte at a time from the low end, with SUB, then SBB and a DAS after each.

Not in 64-bit mode

Opcode 2F raises #UD in 64-bit mode, so the fixture has no case for DAS: the probe runs there and lists the form as not run. GNU as 2.44 and Clang 23 refuse das in 64-bit code, and GCC 14 and Clang 23 have no intrinsic for it. AMD’s Zen 5 guide lists DAS as microcoded, without a latency. Intel’s example for DAS labels its second step DAA.

Forms

Every encoding of DAS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`DAS` not in 64-bit mode DAS	`2F`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = al
c = cf
r = a
cf = 0
if (a & 0xF) > 9 or af:          # the low digit borrowed
    r -= 6
    af = 1
    if a < 6:                    # a borrow out of AL: CF
        cf = 1                   # is set as well
else:
    af = 0
if a > 0x99 or c:                # the high digit, by AL and CF as they
    r -= 0x60                    # were before the instruction
    cf = 1
al = r
sf = r >> 7 & 1
zf = (r & 0xFF) == 0
pf = parity(r)
of = UNDEFINED

Not run on a processor: the instruction does not exist in 64-bit mode, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`DAS` not in 64-bit mode
`AL`	implicit	read, write
`RFLAGS`	implicit	read, write

Flags

T tested, M modified, U undefined; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
U	M	M	TM	M	TM

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Where CF comes from#

Not in 64-bit mode#