DEC

DEC subtracts 1 from its operand and sets the flags as sub x, 1 would, except that CF keeps its value, as after INC. ZF tells when the operand reaches 0, and OF is set only when the smallest negative number wraps to the largest positive one.

Counting down#

DEC followed by JNZ is the classic loop counter: the loop runs until the count reaches 0, with no separate comparison. For do { f(n); } while (--n);, Clang 23 at -O2 counts with dec rbx and jne, GCC 14 with sub rbx, 1 and jne; both set ZF the same way. Because DEC leaves CF alone, the same loop can carry a borrow or carry from one iteration to the next, as Intel’s Optimization Reference Manual shows for a multi-word addition with ADC (Example 3-26). LOOP decrements rCX and jumps in one instruction without touching any flag, but the same manual advises against LOOP and other instructions of more than four micro-ops (Coding Rule 28).

When to use SUB instead#

Keeping CF is a partial write of the flags, which Intel’s manual counts as a cost:

• A shift by CL may leave the flags unchanged, so it must merge with the flags written before it. In Section 3.5.1.5 the manual shows a loop with shl eax, cl and dec edx in which, on Sandy Bridge, the shift runs its slower three-micro-op flow; replacing DEC with SUB, which writes all the flags, lets it run the two-micro-op one.
• Intel’s Table 3-1 (Sandy Bridge) and Table 3-2 (Haswell) fuse DEC with a following jump only for the equal and signed conditions, not for those that read CF. AMD’s guide lists DEC among the instructions that fuse on Zen 5 (Section 2.9.3).

Reference counts#

With LOCK and a memory operand, DEC decrements atomically and ZF says whether the count reached 0, which is what releasing a reference needs. For atomic_fetch_sub(p, 1) == 1, Clang emits lock dec qword ptr [rdi] and sete al, GCC lock sub qword ptr [rdi], 1 and the same SETE. As with INC, the one-byte forms 48h to 4Fh are REX prefixes in 64-bit mode, so DEC is encoded as FF /1 (FE /1 for bytes).

In the optimization guide

What the optimization guide says about DEC, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Front end

• Macro-fusion: Intel’s cores since Sandy Bridge (Skylake) fuse test and and with any conditional branch; cmp, add and sub with branches on the equal, unsigned and signed comparisons, but not on the sign, parity or overflow flag alone; and inc and dec only with branches on equality and the signed comparisons.
• Macro-fusion: AMD’s Zen 3 to Zen 5 fuse more: cmp, test, add, sub, and, or, xor, inc and dec with any conditional branch, except that on Zen 3 and Zen 4 inc and dec do not fuse with a branch that reads the carry flag, which Intel’s cores do not fuse either (Zen 5, Zen 4, Zen 3). sources differ

Out of order

• Partial register and flag writes: Some instructions write only part of the flags: inc and dec leave the carry flag as it was, and bt leaves the zero flag.

Silvermont to Goldmont Plus

• Out-of-order and in-order execution: A branch on the flags of inc or dec costs a cycle more than one on add, sub or cmp.

Skylake to Cooper Lake

• Front end: test and and fuse with any following conditional jump; cmp, add and sub with the jumps on equality and on the unsigned and signed comparisons, but not with js, jp or jo and their inverses; inc and dec only with those on equality and the signed comparisons.

Tremont

• Integer execution: LLVM prefers add and sub to inc and dec on Tremont, where a partial flags write costs a cycle.

Zen 3

• Integer execution: A cmp, test, add, sub, inc, dec, and, or or xor followed by a conditional branch becomes one macro-op, also with a memory operand, unless it carries a displacement together with an immediate, addresses relative to RIP or makes the pair longer than 15 bytes; inc and dec do not fuse with a branch on the carry flag, and jrcxz never fuses.

Zen 4

• Integer execution: A cmp, test, add, sub, inc, dec, and, or or xor followed by a conditional branch becomes one macro-op, also with a memory operand, unless it carries a displacement together with an immediate, addresses relative to RIP or makes the pair longer than 15 bytes; inc and dec do not fuse with a branch on the carry flag.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()                  # with LOCK: one atomic read-modify-write
r = low(a - 1)
if not nf:                       # NF=1 (APX) leaves the flags as they were
    of = a == 1 << (OSIZE - 1)   # the smallest negative number wrapped
    sf = msb(r)
    zf = r == 0
    af = (a & 0xF) == 0          # a borrow into bit 3
    pf = parity(r)
    # CF keeps its value, unlike after SUB dest, 1
dest.write(r)                    # a 32-bit register: bits 63:32 cleared

a = src.read()
r = low(a - 1)
if not nf:                       # NF=1 leaves the flags as they were
    of = a == 1 << (OSIZE - 1)   # the smallest negative number wrapped
    sf = msb(r)
    zf = r == 0
    af = (a & 0xF) == 0          # a borrow into bit 3
    pf = parity(r)
    # CF keeps its value
dest.write(r)                    # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

Attributes

What else XED records about the forms. How to read.

Legacy memory forms without LOCK

accepts a LOCK prefix

LOCK forms

locked: atomic read-modify-write; accepts XACQUIRE; accepts XRELEASE

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• BTR
• BTS
• CALL
• CBW
• CDQ
• CDQE
• CLC
• CLD
• CLI
• CMC
• CMP
• CMPS
• CMPXCHG
• CMPXCHG8B
• CPUID
• CQO
• CWD
• CWDE
• DAA
• DAS
• DIV
• ENTER
• IDIV
• IMUL
• IN
• INC
• INS
• INT
• INT1
• INT3
• INTO
• IRET
• Jcc
• JCXZ
• JECXZ
• JMP
• JRCXZ
• LDS
• LEA
• LEAVE

All 109 General-purpose instructions

More APX instructions

• AAND
• ADC
• ADCX
• ADD
• ADOX
• AND
• ANDN
• AOR
• AXOR
• BEXTR
• BLSI
• BLSMSK
• BLSR
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI
• MOVRS

All 88 APX instructions