DIV

DIV divides an unsigned dividend twice the operand’s width by the operand: RDX:RAX by a 64-bit divisor, EDX:EAX by a 32-bit one, DX:AX by a 16-bit one, and AX by a byte. The quotient goes to the low half (rAX, or AL) and the remainder to the high half (rDX, or AH), so one DIV yields both a / b and a % b; GCC 14 and Clang 23 at -O2 compile a function that needs both to a single DIV.

Setting up the dividend#

Dividing one register by another needs a zero upper half: compilers emit xor edx, edx before div rsi, and for bytes they load the dividend with movzx eax, dil, which clears AH. Signed division is IDIV, after CQO, CDQ or CWD has copied the sign of rAX into every bit of rDX.

Divide errors#

DIV raises #DE in two cases: a divisor of 0, and a quotient too wide for the low half, which happens exactly when the upper half of the dividend is not less than the divisor, so a stale value left in RDX gives a wrong result at best and #DE at worst. #DE is a fault: the saved RIP points at the DIV itself, and a handler that returns without changing anything runs it again. Zen 5 raised #DE in the recorded cases of both kinds. Linux 7.3 hands #DE to the program as SIGFPE with si_code FPE_INTDIV, which shells report as “Floating point exception”, the name of that signal, although no floating point is involved.

Division by a constant#

When the divisor is known at compile time, compilers avoid DIV and multiply by a scaled reciprocal instead and keep the high bits of the product. GCC 14 and Clang 23 compile x / 10 for a 32-bit unsigned x to a multiplication by 0xCCCCCCCD, which is 2^35 / 10 rounded up, followed by a right shift by 35; the result equals the quotient for every 32-bit x. A power of two needs only a shift: SHR for unsigned values, and for signed ones SAR after a correction that makes the division round toward zero (see CMOVcc).

In the optimization guide

What the optimization guide says about DIV, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Bulldozer to Excavator

• Integer execution: DIV and IDIV are microcoded, and their time grows with the width of the dividend’s value on Bulldozer and of the quotient’s from Piledriver on, up to 76 and 72 cycles for 64-bit operands, so a division by a constant is best done by multiplying. sources differ

Golden Cove and Raptor Cove

• Integer execution: Integer division runs on port 1; LLVM’s models give a 32-bit DIV 15 cycles and a 64-bit one 18, the latter three micro-ops that keep port 1 busy for three cycles.

Haswell and Broadwell

• Integer execution and bypass: A 64-bit integer divide is much slower than a 32-bit one, so LLVM, tuning for Haswell or Broadwell, uses the 32-bit divide when both 64-bit operands turn out positive and below 2^32. sources differ

Ice Lake to Rocket Lake

• Integer execution: A new integer divider on port 1 makes DIV and IDIV much faster than on Skylake, in latency and in throughput; neither Intel nor Agner Fog gives numbers. sources differ

Jaguar and Puma

• Integer execution: The radix-4 divider produces two quotient bits a cycle: AMD’s spreadsheet gives DIV and IDIV at most 25 cycles with 32-bit operands and 41 with 64-bit ones, ending early when the quotient is small. sources differ

Sandy Bridge and Ivy Bridge

• Integer and vector execution: One divider, on port 0, serves integer division and also the square root and floating-point division operations, so only one of them runs at a time; LLVM’s model gives an 8-, 16-, 32- or 64-bit integer divide the same 25-cycle latency and a throughput of one every 10 cycles.

Silvermont to Goldmont Plus

• Out-of-order and in-order execution: Division is microcoded and slow on Silvermont, up to 135 cycles at 64 bits; Goldmont takes 11 to 41. sources differ

Skylake to Cooper Lake

• Integer execution: Integer division is slow: LLVM’s models give a 64-bit DIV 76 cycles and 32 micro-ops and a 64-bit IDIV 102 cycles, against 18 on Golden Cove.

Zen and Zen+

• Integer execution: The divider, on ALU 2, yields two bits of the quotient a cycle: AMD’s spreadsheet gives a 64-bit DIV 41 cycles and a 32-bit one 25, as LLVM’s model does.

Zen 2

• Integer execution: The divider produces two bits of the quotient a cycle, so division is slow: AMD’s spreadsheet gives a 64-bit DIV 41 cycles and a 32-bit one 25, as LLVM’s model does, far more than on Zen 3.

Zen 3

• Integer execution: Division runs on ALU 0 and takes about 8 cycles plus 1 for every 9 bits of the quotient, and a typical 64-bit division can start every 8 cycles. sources differ

Zen 4

• Integer execution: xor edx, edx before DIV, or CDQ or CQO before IDIV, with the same operand size and a divisor in a register other than rDX, saves a macro-op: the pair is dispatched as one fewer.
• Integer execution: Division takes about 8 cycles plus 1 for every 9 bits of the quotient, and a typical 64-bit division can start every 8 cycles. sources differ

Zen 5

• Integer execution: Division takes about 8 cycles plus 1 for every 9 bits of the quotient, and a typical 64-bit division can start every 8 cycles.

Vulnerability mitigations

Mitigations of these processor vulnerabilities use DIV:

• CVE-2023-20588: Speculative Division by Zero

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

d = src.read()
if d == 0:
    fault(DE)                    # a divide by zero
if OSIZE == 8:
    n = ax                       # the dividend: AX, DX:AX, EDX:EAX or
else:                            # RDX:RAX
    n = rDX << OSIZE | rAX
q = n // d
if q >> OSIZE != 0:
    fault(DE)                    # the quotient does not fit in rAX
if OSIZE == 8:
    al = q
    ah = n % d                   # the remainder
else:                            # EAX and EDX: bits 63:32 cleared
    rAX = q
    rDX = n % d                  # the remainder
if not nf:                       # NF=1 (APX) leaves the flags as they were
    of = sf = zf = af = pf = cf = UNDEFINED

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• BTS
• CALL
• CBW
• CDQ
• CDQE
• CLC
• CLD
• CLI
• CMC
• CMP
• CMPS
• CMPXCHG
• CMPXCHG8B
• CPUID
• CQO
• CWD
• CWDE
• DAA
• DAS
• DEC
• ENTER
• IDIV
• IMUL
• IN
• INC
• INS
• INT
• INT1
• INT3
• INTO
• IRET
• Jcc
• JCXZ
• JECXZ
• JMP
• JRCXZ
• LDS
• LEA
• LEAVE
• LES

All 109 General-purpose instructions

More APX instructions

• ADC
• ADCX
• ADD
• ADOX
• AND
• ANDN
• AOR
• AXOR
• BEXTR
• BLSI
• BLSMSK
• BLSR
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI
• MOVRS
• MUL

All 88 APX instructions