DIVPD instruction (SSE2)

DIVPD divides the two doubles of its first operand by those of its second, each quotient correctly rounded under MXCSR. VDIVPD is the VEX and EVEX form; its page tells the invalid 0/0 from a division by zero and explains why compilers keep dividing doubles even with -ffast-math, and DIVPS gives the history of the divider’s speed. The legacy SSE2 encoding writes the quotients over the dividends, keeps bits 128 and up of the register (see SSE and AVX) and needs a memory operand aligned to 16 bytes.

Zen 5’s recorded cases show that the signs of two zeros do not matter. divpd xmm4, xmm4, with 0.5 and 0 in XMM4, divided each by itself to 1 and to the indefinite FFF8000000000000H, setting IE. With MXCSR at FFC0H (round toward zero, FTZ and DAZ set), 0 / -0 and -0 / -0, the divisors read from memory, both gave the same indefinite, whose sign bit is set whatever the operands’ signs, and set IE again.

Dividing into a constant

SSE has no estimate of a double’s reciprocal: RCPPS and its kin work on singles, and VRCP14PD arrived with AVX-512. So baseline code divides. In our builds at -O2 for the default target, GCC 14 and Clang 23 compile a[i] = b[i] / c[i] and b[i] / 3.0 over global arrays of doubles to DIVPD, the first with c read from memory; only b[i] / 4.0, whose reciprocal is exact, becomes MULPD by 0.25. For 1.0 / b[i] the constant is the dividend, which the instruction overwrites, so both compilers keep a vector of ones in a register and copy it with MOVAPD before each division.

AMD’s latency spreadsheet for Zen 5 gives DIVPD the figures of VDIVPD: a latency of 13 cycles and 0.25 per cycle, on pipe FP1, against 10 cycles and 0.4 for DIVPS. Two doubles per instruction make that half a quotient per cycle at most.

In the optimization guide

What the optimization guide says about DIVPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Bulldozer to Excavator

Vectors and floating point: Division and square root run in each FMA unit’s own divider: DIVPD takes 27 cycles and SQRTPD 38 on Bulldozer and Piledriver, while AMD’s table for Steamroller gives single precision fewer cycles, 18 for DIVPS, and double precision more, 33 and 44. sources differ

Silvermont to Goldmont Plus

Vectors and cryptography: Division is slow on Silvermont and Goldmont; Goldmont Plus divides two to three times faster.

Skylake to Cooper Lake

Vectors on all parts: Division and square root are pipelined, and 256-bit forms have the latency of 128-bit ones: LLVM’s models give DIVPS 11 cycles, SQRTPS 12, DIVPD 14 and SQRTPD 18.

Forms

Every encoding of DIVPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`DIVPD xmm, m128` DIVPD_XMMpd_MEMpd	`66 0F 5E /r`	SSE2
`DIVPD xmm, xmm` DIVPD_XMMpd_XMMpd	`66 0F 5E /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each double of the result comes from the double in the same place in each source.

Result double i comes from double i of xmm1 and xmm2. Result doubles 1 to 0: a1/b1, a0/b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    a = xmm1.f64[i]
    b = src2.f64[i]
    xmm1.f64[i] = div(a, b)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`DIVPD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to DIVPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_div_pd` `__m128d _mm_div_pd(__m128d __a, __m128d __b)`	`DIVPD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Dividing into a constant#