DIVPS instruction (SSE)

DIVPS divides four pairs of singles, each quotient rounded once as MXCSR says; DIVSS divides the lowest pair and VDIVPS is the VEX and EVEX form. Two special cases are easy to confuse, and the recordings from Zen 5 show the second:

A nonzero number divided by zero is a division by zero: it sets ZE and, with the exception masked, gives an infinity with the sign of the quotient.
Zero divided by zero, and an infinity by an infinity, are invalid operations instead. They set IE, not ZE, and give the QNaN floating-point indefinite, FFC00000H, whatever the signs.

Speed

Intel’s optimization guide puts DIVPS at about 14 cycles on its processors before Skylake, with the next division unable to start until it is done, and the 256-bit VDIVPS of Sandy Bridge, which runs on a 128-bit data path, at twice that; on Skylake both widths take the same time and are pipelined (Section 15.12). AMD’s guide for Zen 5 sends all divisions and square roots to one unit, which can have two in flight (Section 2.11.1).

So compilers avoid DIVPS where the result stays the same: GCC 14 and Clang 23 at -O2 compile x / 2.0f to a multiplication by 0.5, which gives identical bits, but keep x / 3.0f a division, since 1/3 has no exact binary value. With -ffast-math they multiply by the rounded 1/3 instead, and both compile a vectorized a[i] = b[i] / c[i] to RCPPS, an estimate of 1/c[i], followed by a Newton-Raphson step and a multiplication. Intel’s guide gives such a sequence about 22 correct bits of the 24 (Section 15.12), so its results can differ from DIVPS’s in the last bits; the guide also shows that on Skylake the sequence is not always the faster one.

In the optimization guide

What the optimization guide says about DIVPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Jaguar and Puma

Vectors and floating point: Division and square root iterate in the multiply unit of pipe 1, not pipelined and without early exit: DIVSS takes 14 cycles, DIVPS, DIVPD and DIVSD 19, SQRTSS 16, SQRTPS 21 and SQRTPD 27, and a 256-bit form twice as long. sources differ

Silvermont to Goldmont Plus

Vectors and cryptography: Division is slow on Silvermont and Goldmont; Goldmont Plus divides two to three times faster.

Skylake to Cooper Lake

Vectors on all parts: Division and square root are pipelined, and 256-bit forms have the latency of 128-bit ones: LLVM’s models give DIVPS 11 cycles, SQRTPS 12, DIVPD 14 and SQRTPD 18.

Forms

Every encoding of DIVPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`DIVPS xmm, m128` DIVPS_XMMps_MEMps	`NP 0F 5E /r`	SSE
`DIVPS xmm, xmm` DIVPS_XMMps_XMMps	`NP 0F 5E /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.

Result single i comes from single i of xmm1 and xmm2. Result singles 3 to 0: a3/b3, a2/b2, a1/b1, a0/b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    a = xmm1.f32[i]
    b = src2.f32[i]
    xmm1.f32[i] = div(a, b)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 9 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`DIVPS xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to DIVPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_div_ps` `__m128 _mm_div_ps(__m128 __a, __m128 __b)`	`DIVPS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Speed#