DIVSD instruction (SSE2)

DIVSD divides the low double of its destination by the low double of its source and keeps the high double. It is SSE2’s scalar form of DIVPD; DIVSS shows which divisions compilers turn into multiplications, and ADDSS covers what the scalar forms share. GCC 14 and Clang 23 at -O2 compile a / b over double to divsd xmm0, xmm1, and a mean, s / n with an int n, to CVTSI2SD and DIVSD. Zen 5’s two recorded cases:

With MXCSR at FFC0H (round toward zero, FTZ and DAZ set), 10^-300 divided by itself from memory gave exactly 1 and set no flag.
Under MXCSR’s default, 1F80H, -infinity divided by 1 gave -infinity. The high doubles held the largest denormal in the destination and a negative denormal in the source, yet DE stayed clear: only the low element takes part.

No estimate for doubles

x / 10.0 stays a DIVSD in our builds, since 0.1 has no exact double; -ffast-math turns it into a MULSD by 0.1, whose product can differ from the quotient in the last bit. A reciprocal, 1.0 / x, stays DIVSD with or without that option: SSE2 has no reciprocal estimate for doubles, as DIVPD’s page explains.

What -ffast-math does change is a loop that divides by one value: da[i] = db[i] / s over global arrays becomes a single DIVSD of 1 by s before the loop and MULPD by its result inside, where the default build runs a DIVPD for every two elements. The quotients then carry two roundings instead of one.

AMD’s latency spreadsheet for Zen 5 lists it at 13 cycles and 0.25 per cycle on pipe FP1, against 10 cycles and 0.4 for DIVSS. The memory form reads eight bytes at any alignment, the legacy form keeps bits 255:128 (see mixing SSE and AVX), and VDIVSD is the VEX and EVEX form.

In the optimization guide

What the optimization guide says about DIVSD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Silvermont to Goldmont Plus

Vectors and cryptography: Division is slow on Silvermont and Goldmont; Goldmont Plus divides two to three times faster.

Zen and Zen+

Vectors and floating point: Division and square root run on pipe 3: AMD’s spreadsheet gives divps 10 cycles, DIVSD 13, sqrtss 14 and SQRTSD 20, as LLVM’s model does, and LLVM tunes -march=znver1 to compute square roots with these instructions rather than an estimate.

Forms

Every encoding of DIVSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`DIVSD xmm, m64` DIVSD_XMMsd_MEMsd	`F2 0F 5E /r`	SSE2
`DIVSD xmm, xmm` DIVSD_XMMsd_XMMsd	`F2 0F 5E /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low double is computed; the other double comes from xmm1.

Result double 0 is computed from double 0 of xmm1 and xmm2; double 1 is that of xmm1. Result doubles 1 to 0: a1, a0/b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f64[0] = div(xmm1.f64[0], src2.f64[0])
# xmm1.q[1] keeps its value
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`DIVSD xmm, xmm/m64`
`xmm`	explicit	read, write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to DIVSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_div_sd` `__m128d _mm_div_sd(__m128d __a, __m128d __b)`	`DIVSD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

No estimate for doubles#