DIVSS instruction (SSE)

DIVSS divides the low single of its destination by the low single of its source and keeps singles 1 to 3 of the destination. It is the scalar form of DIVPS, whose page tells a division by zero from the invalid 0/0 and gives the history of the divider’s speed; ADDSS covers what the scalar forms share, from the kept elements to the memory operand of four bytes at any alignment. GCC 14 and Clang 23 at -O2 compile a / b over float to divss xmm0, xmm1. In Zen 5’s two recorded cases:

With MXCSR at FFC0H (round toward zero, FTZ and DAZ set), the largest denormal divided by the denormal -2^-127 from memory was 0/0 to the processor: DAZ read both as zeros, and the result was the indefinite FFC00000H with IE set, where the true quotient is about -2.
Under MXCSR’s default, 1F80H, -1 divided by +infinity gave -0 and set no flag.

Dividing by a constant

A division whose divisor has an exact reciprocal is a multiplication: in our builds x / 2.0f is a MULSS by 0.5, and the mean of 1,024 floats, s / 1024, a MULSS by 2^-10. x / 3.0f stays DIVSS, and only -ffast-math turns it into a MULSS by 0.333333343, which can round differently.

A reciprocal, 1.0f / x, needs the 1 as the dividend, so both compilers load it with MOVSS and add a MOVAPS, as for 1.0f - x on SUBSS’s page. Even with -ffast-math neither uses the estimate RCPSS for it at the x86-64 baseline. In a loop with -ffast-math, fa[i] = fb[i] / s becomes one DIVSS of 1 by s before the loop and MULPS inside it, where the default build divides every vector with DIVPS.

AMD’s latency spreadsheet for Zen 5 lists DIVSS at 10 cycles and 0.4 per cycle on pipe FP1, the figures of DIVPS: its one divide unit also takes every square root (Section 2.11.1). The legacy form keeps bits 255:128 (see mixing SSE and AVX), and VDIVSS is the VEX and EVEX form.

In the optimization guide

What the optimization guide says about DIVSS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Jaguar and Puma

Vectors and floating point: Division and square root iterate in the multiply unit of pipe 1, not pipelined and without early exit: DIVSS takes 14 cycles, DIVPS, DIVPD and DIVSD 19, SQRTSS 16, SQRTPS 21 and SQRTPD 27, and a 256-bit form twice as long. sources differ

Silvermont to Goldmont Plus

Vectors and cryptography: Division is slow on Silvermont and Goldmont; Goldmont Plus divides two to three times faster.

Forms

Every encoding of DIVSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`DIVSS xmm, m32` DIVSS_XMMss_MEMss	`F3 0F 5E /r`	SSE
`DIVSS xmm, xmm` DIVSS_XMMss_XMMss	`F3 0F 5E /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low single is computed; the other singles come from xmm1.

Result single 0 is computed from single 0 of xmm1 and xmm2; singles 3 to 1 are those of xmm1. Result singles 3 to 0: a3, a2, a1, a0/b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f32[0] = div(xmm1.f32[0], src2.f32[0])
# xmm1.d[1] to [3] keep their values
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`DIVSS xmm, xmm/m32`
`xmm`	explicit	read, write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to DIVSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_div_ss` `__m128 _mm_div_ss(__m128 __a, __m128 __b)`	`DIVSS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Dividing by a constant#