DPPD instruction (SSE4.1)

DPPD is the double-precision form of DPPS: it multiplies the two pairs of doubles, adds the two products and writes the sum to the elements of the destination that the immediate selects, zeroing the others. With only two elements, the immediate uses two bits at each end: bits 5:4 choose the products, a product left out counting as +0.0, and bits 1:0 the elements that receive the sum. DPPS’s page covers the rest that the two share, from the cost of a horizontal sum to the gathering of many dot products. Two Zen 5 cases show both ends:

dppd xmm4, xmmword ptr [mem], 31h with 3.0 and 2.0 against 0.1 and -1.0 gave -1.7 in the low double and +0 in the high one, and set PE, since the sum is inexact;
with an immediate of 0, the product of -DBL_MAX and 2.0 would have overflowed, but it was never formed: both doubles became +0 and no MXCSR flag was set.

In compiled code

With two products and one sum, DPPD rounds as C’s a[0]*b[0] + a[1]*b[1] does, yet compilers do not use it for that expression. GCC 14 and Clang 23 at -O2 with -march=x86-64-v2 compile it to two MULSDs and an ADDSD, or under -ffast-math to MULPD, UNPCKHPD and an add. With -march=x86-64-v3 both contract it to a VMULSD and a VFMADD231SD, whose single rounding of one product and the sum can give a different last bit from DPPD. Only _mm_dp_pd produces the instruction, in both.

AMD’s latency spreadsheet for Zen 5 lists the register form as three macro-ops with a latency of 7 cycles, and the memory form as microcoded. As a legacy SSE instruction with a full 128-bit memory operand, it needs that operand aligned to 16 bytes, and it keeps bits 255:128 of its register (see mixing SSE and AVX). VDPPD, the VEX form, has no 256-bit version, unlike VDPPS, and AVX-512 has no EVEX form.

Forms

Every encoding of DPPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`DPPD xmm, m128, imm8` DPPD_XMMdq_MEMdq_IMMb	`66 0F 3A 41 /r ib`	SSE4.1
`DPPD xmm, xmm, imm8` DPPD_XMMdq_XMMdq_IMMb	`66 0F 3A 41 /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Dot product: the products of the doubles that imm8[5:4] selects are summed, and the sum goes to the doubles that imm8[1:0] selects; the others are 0.

Example: imm8 = 0x31 (0011 0001 in binary). Under each element: its bit of imm8[7:4], then of imm8[3:0].

With imm8 = 0x31, result doubles 1 to 0: 0, sum.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

zero = to_f64(0)
if imm8 >> 4 & 1:
    p0 = mul(xmm1.f64[0], src2.f64[0])
else:
    p0 = zero
if imm8 >> 5 & 1:
    p1 = mul(xmm1.f64[1], src2.f64[1])
else:
    p1 = zero
x = add(p0, p1)
for i in range(2):
    if imm8 >> i & 1:
        xmm1.f64[i] = x
    else:
        xmm1.f64[i] = zero
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`DPPD xmm, xmm/m128, imm8`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2D

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to DPPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_dp_pd` `__m128d _mm_dp_pd(__m128d X, __m128d Y, const int M)`	`DPPD xmm, xmm, imm8` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

In compiled code#