DPPS instruction (SSE4.1)

DPPS computes a dot product of two vectors of four singles in one instruction, with the immediate in charge of both ends. Its high four bits choose which element pairs are multiplied; a pair left out counts as +0.0. Its low four bits choose which elements of the destination get the sum; the others are set to zero. dpps xmm0, xmm1, 0F1h is the full four-element dot product into the low element, and 7Fh the dot product of three components (x, y, z without w), copied into all four elements, ready to scale each component of a vector by it.

Rounding steps

Each product is rounded to single, and the sums are formed in pairs: elements 0 and 1, elements 2 and 3, then the two sums, each rounded in turn. C’s a[0]*b[0] + a[1]*b[1] + a[2]*b[2] + a[3]*b[3] adds from left to right, which can round differently, so the compilers do not substitute DPPS for it. GCC 14 and Clang 23 at -O2 with -msse4.1 compile that expression to scalar MULSS and ADDSS; with -ffast-math they use one MULPS and two rounds of shuffles and adds, still without DPPS. Only the intrinsic _mm_dp_ps gives DPPS, in both.

On Zen 5 a pair that the immediate leaves out took no part at all: an SNaN, or infinity times zero, in such a pair raised nothing, even with the exceptions unmasked. With the low four bits clear, the result was all zeros but the products and sums still set the flags, PE among them. Two products of FLT_MAX in elements 0 and 2 overflowed in the last sum.

Cost

Intel’s optimization manual compares one dot product by MULPS and shuffles, by HADDPS and by DPPS, and finds DPPS the fastest in the Enhanced Intel Core microarchitecture, the first with SSE4.1; for many dot products it suggests gathering the results with INSERTPS (Section 7.6.1). AMD’s Zen 5 guide lists the register form as eight macro-ops with a latency of 11 cycles, and the memory form as microcoded. Code over many vectors avoids the horizontal sum: with one array per component, MULPS and ADDPS, or VFMADD231PS, compute four dot products at once.

DPPD does the same for two doubles. VDPPS has a 256-bit form that computes two independent dot products, one in each 128-bit half; VDPPD has none, and AVX-512 has no EVEX form of either.

Forms

Every encoding of DPPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`DPPS xmm, m128, imm8` DPPS_XMMdq_MEMdq_IMMb	`66 0F 3A 40 /r ib`	SSE4.1
`DPPS xmm, xmm, imm8` DPPS_XMMdq_XMMdq_IMMb	`66 0F 3A 40 /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Dot product: the products of the singles that imm8[7:4] selects are summed, and the sum goes to the singles that imm8[3:0] selects; the others are 0.

Example: imm8 = 0x71 (0111 0001 in binary). Under each element: its bit of imm8[7:4], then of imm8[3:0].

With imm8 = 0x71, result singles 3 to 0: 0, 0, 0, sum.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

zero = to_f32(0)
if imm8 >> 4 & 1:
    p0 = mul(xmm1.f32[0], src2.f32[0])
else:
    p0 = zero
if imm8 >> 5 & 1:
    p1 = mul(xmm1.f32[1], src2.f32[1])
else:
    p1 = zero
if imm8 >> 6 & 1:
    p2 = mul(xmm1.f32[2], src2.f32[2])
else:
    p2 = zero
if imm8 >> 7 & 1:
    p3 = mul(xmm1.f32[3], src2.f32[3])
else:
    p3 = zero
x = add(add(p0, p1), add(p2, p3))
for i in range(4):
    if imm8 >> i & 1:
        xmm1.f32[i] = x
    else:
        xmm1.f32[i] = zero
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 25 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`DPPS xmm, xmm/m128, imm8`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2D

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to DPPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_dp_ps` `__m128 _mm_dp_ps(__m128 X, __m128 Y, const int M)`	`DPPS xmm, xmm, imm8` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Rounding steps#

Cost#