EMMS instruction (MMX)

EMMS, 0F 77, ends a stretch of MMX code by tagging all eight x87 registers empty. The eight MMX registers MM0 to MM7 are the low 64 bits of the x87 registers, and every other MMX instruction sets TOP to 0 and tags all eight registers valid. Without EMMS, x87 code that follows finds a full stack: its first load is a stack overflow, which with IE masked pushes the QNaN indefinite instead of the value. SSE and AVX code on XMM registers is not affected and needs no EMMS. FEMMS is AMD’s 3DNow! instruction of the same effect.

On Zen 5

EMMS tagged every register empty and kept their bits, as both manuals say, and kept C0 to C3. It also set TOP to 0: from a stack whose TOP was 3, the registers came out renumbered from physical register 0, where Intel’s manual only changes the tag word. Like the x87 instructions, EMMS checks for a pending unmasked x87 exception: with IE flagged, unmasked and ES set, Zen 5 raised #MF and changed nothing.

In compiled code

C reaches EMMS through the intrinsic _mm_empty(), and compilers emit it only there: GCC 14 and Clang 23 at -O2 add none at the end of MMX code by themselves. In 64-bit code both now carry out the MMX intrinsics with SSE2 on XMM registers, so _mm_add_pi16 becomes paddw xmm0, xmm1 and no MMX register is touched, yet _mm_empty() still becomes an EMMS: after the PADDW with GCC, before it with Clang. In 32-bit code GCC with -march=pentium-mmx uses MM0 and MM1, where the EMMS matters; Clang 23 refuses the MMX intrinsics there unless SSE2 is enabled, and then uses XMM registers as well.

Intel’s optimization manual advises an EMMS at the end of MMX code that x87 code may follow, none where the next instruction uses MMX again, and keeping x87 and MMX code apart so that loops need none; it recommends replacing MMX code with 128-bit SIMD code, which also does away with EMMS (Section 6.2).

AMD’s Zen 5 guide lists EMMS as one macro-op, six per cycle.

Forms

Every encoding of EMMS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`EMMS` EMMS	`NP 0F 77`	MMX

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

ftw = 0xFFFF                         # every register empty, its value
                                     # kept
top = 0                              # Zen 5's; Intel's manual changes
                                     # the tags only

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

None: XED lists no operands for this form.

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to EMMS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_empty` `void _mm_empty(void)`	`EMMS` Legacy -mmmx

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

On Zen 5#

In compiled code#