ENCLS instruction (SGX)

Forms

Every encoding of ENCLS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ENCLS` ENCLS	`NP 0F 01 CF`	SGX

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`ENCLS`
Skylake, Skylake-SP, Ice Lake, Sapphire Rapids	100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

sgx1 = cpuid_leaf(0x12, 0)[0] & 1
if in_smm or not sgx1:
    fault(UD)
if CPL > 0:
    fault(UD)                    # #UD, not #GP
if vmx_nonroot:
    p = current_vmcs
    pri = vmcs_read(p, 0x4002)   # processor-based controls; bit
    sec = 0                      # 31 activates the secondary ones
    if pri >> 31:
        sec = vmcs_read(p, 0x401E)
    if sec >> 15 & 1:            # ENCLS exiting: the leaf's bit,
        bm = vmcs_read(p, 0x202E)  # bit 63 for those past 62
        if bm >> min(eax, 63) & 1:
            vm_exit(60)
fc = msr[IA32_FEATURE_CONTROL]
if not fc & 1 or not fc >> 18 & 1:
    fault(GP, 0)                 # SGX not enabled: lock, bit 18
if not leaf_exists(eax):
    fault(GP, 0)
if not cr0 >> 31 & 1:
    fault(GP, 0)                 # paging off
leaf_function(eax)               # ECREATE (0), EADD (1), EINIT (2)
                                 # ... each with its own checks,
                                 # and flags as its page says

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no SGX, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ENCLS`
`EAX`	implicit	read
`RBX`	implicit	conditional read, write
`RCX`	implicit	conditional read, write
`RDX`	implicit	conditional read, write

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: privileged: CPL 0 only

Leaf functions

ENCLS performs the leaf function whose number is in EAX; each has a page of its own. Only the operating system (CPL 0) may run ENCLS. The Linux kernel's headers give every number but ELDB's, which Linux does not use, and Intel's SGX SDK the first seven; ELDB's number is the one the manual gives.

EAX	Leaf function	Summary	Requires
`00H`	`ECREATE`	Starts building an enclave by copying its control structure, the SECS, from ordinary memory into a page of the EPC.	SGX1
`01H`	`EADD`	Copies a page from ordinary memory into the EPC for an enclave being built, and adds its offset and attributes to the enclave's measurement.	SGX1
`02H`	`EINIT`	Completes the build of an enclave: checks its signed SIGSTRUCT and launch token, fixes its measurement and makes it ready for EENTER.	SGX1
`03H`	`EREMOVE`	Removes a page from the EPC, detaching it from its enclave and marking it unused.	SGX1
`04H`	`EDBGRD`	Reads eight bytes (four outside 64-bit mode) of a debug enclave's memory, at the address in RCX, into RBX.	SGX1
`05H`	`EDBGWR`	Writes RBX (EBX outside 64-bit mode) to a debug enclave's memory at the address in RCX.	SGX1
`06H`	`EEXTEND`	Adds 256 bytes of a page of an enclave being built to the enclave's measurement, MRENCLAVE.	SGX1
`07H`	`ELDB`	Loads a page that EWB wrote out back into the EPC, checking and decrypting it, and marks it blocked.	SGX1
`08H`	`ELDU`	Loads a page that EWB wrote out back into the EPC, checking and decrypting it, and leaves it unblocked.	SGX1
`09H`	`EBLOCK`	Marks an EPC page as blocked, the first step of evicting it from the EPC.	SGX1
`0AH`	`EPA`	Turns an EPC page into a version array, which holds the versions of pages evicted from the EPC.	SGX1
`0BH`	`EWB`	Evicts a blocked EPC page: encrypts it, writes it to ordinary memory and keeps its version in a version array.	SGX1
`0CH`	`ETRACK`	Starts tracking the TLB flushes that must follow EBLOCK before the blocked pages of an enclave can be evicted.	SGX1
`0DH`	`EAUG`	Adds a zeroed page to an enclave that is already running; the enclave must accept it with EACCEPT or EACCEPTCOPY.	SGX2
`0EH`	`EMODPR`	Restricts the access rights of a page of a running enclave, which then accepts the change with EACCEPT.	SGX2
`0FH`	`EMODT`	Changes the type of a page of a running enclave, to trim it for example, which then accepts the change with EACCEPT.	SGX2
`18H`	`EUPDATESVN`	Updates the SGX security version of the processor to that of the loaded microcode update, when the EPC holds no valid page.	EUPDATESVN

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SGX` SGX	SGX `CPUID.(EAX=07H,ECX=0):EBX[2]` SGX	Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont Plus

ENCLS