Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of ENCLU that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
ENCLU ENCLUNP 0F 01 D7SGX

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
ModelENCLU
Skylake, Skylake-SP, Ice Lake, Sapphire Rapids100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

sgx1 = cpuid_leaf(0x12, 0)[0] & 1
if in_smm or not sgx1:
    fault(UD)
if cr0 >> 3 & 1:
    fault(NM)                    # CR0.TS
if CPL < 3:
    fault(UD)                    # CPL 3 alone
fc = msr[IA32_FEATURE_CONTROL]
if not fc & 1 or not fc >> 18 & 1:
    fault(GP, 0)                 # SGX not enabled: lock, bit 18
if not leaf_exists(eax):
    fault(GP, 0)
if not cr0 >> 31 & 1 or not cr0 >> 5 & 1:
    fault(GP, 0)                 # paging off, or CR0.NE clear
entry = eax in (2, 3)            # EENTER, ERESUME
if enclave_mode == entry:
    fault(GP, 0)                 # those enter an enclave from
                                 # outside, the others run inside
leaf_function(eax)               # each with its own checks, and
                                 # flags as its page says
# with CET's indirect branch tracking waiting for an ENDBRANCH, any
# leaf but ERESUME first raises #CP

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no SGX, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
ENCLU
EAXimplicitread
RBXimplicitconditional read, write
RCXimplicitconditional read, write
RDXimplicitconditional read, write

Flags

None: XED records no flag that the forms test or change.

Leaf functions

ENCLU performs the leaf function whose number is in EAX; each has a page of its own. Only applications (CPL 3) may run ENCLU. Intel's SGX SDK gives all ten numbers, Open Enclave the first eight. Intel's future-extensions reference (319433-062) adds EREPORT2 and EGETKEY256, for 256-bit keys, which the manual does not document yet.

EAXLeaf functionSummaryRequires
00HEREPORTCreates a report of the running enclave that a target enclave on the same platform can verify, for local attestation.SGX1
01HEGETKEYReturns a 128-bit key from the processor's key hierarchy, such as a sealing key, as a KEYREQUEST structure asks.SGX1
02HEENTEREnters an enclave through one of its thread control structures (TCS), at the entry point that the TCS gives.SGX1
03HERESUMERe-enters an enclave that an exception or interrupt left, with the state saved in its SSA frame.SGX1
04HEEXITLeaves the running enclave and continues at the address in RBX, outside it.SGX1
05HEACCEPTLets a running enclave accept a change that system software made to one of its pages with EAUG, EMODT or EMODPR.SGX2
06HEMODPEExtends the access rights of a page of the running enclave, which the enclave may do by itself.SGX2
07HEACCEPTCOPYInitializes a page that EAUG added by copying another page of the enclave into it, and accepts it.SGX2
08HEVERIFYREPORT2Checks, inside an enclave, the MAC of a report that a TDX trust domain created with SEAMREPORT.EVERIFYREPORT2
09HEDECCSSADecrements the index of the current SSA frame (TCS.CSSA) of the enclave thread, from inside the enclave.EDECCSSA

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

More SGX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026): Volume 3D, page 41-10 (ENCLU)
  4. Intel SGX SDK 2.25: common/inc/internal/inst.h (ENCLU and ENCLS leaf numbers, BSD license)
  5. Open Enclave SDK: include/openenclave/bits/sgx/sgxtypes.h (ENCLU leaf numbers, MIT license)
  6. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.