Instruction
ENCLU
Performs the SGX leaf function for applications and enclaves that EAX selects, such as EENTER or EGETKEY; only CPL 3 may run it.
- Extensions
- Forms
- 1 (1 Legacy)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
ENCLU
ENCLU | NP 0F 01 D7 | SGX |
Latency and throughput
| Model | ENCLU |
|---|---|
| Skylake, Skylake-SP, Ice Lake, Sapphire Rapids | 100 / 0.25p0156 |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
sgx1 = cpuid_leaf(0x12, 0)[0] & 1
if in_smm or not sgx1:
fault(UD)
if cr0 >> 3 & 1:
fault(NM) # CR0.TS
if CPL < 3:
fault(UD) # CPL 3 alone
fc = msr[IA32_FEATURE_CONTROL]
if not fc & 1 or not fc >> 18 & 1:
fault(GP, 0) # SGX not enabled: lock, bit 18
if not leaf_exists(eax):
fault(GP, 0)
if not cr0 >> 31 & 1 or not cr0 >> 5 & 1:
fault(GP, 0) # paging off, or CR0.NE clear
entry = eax in (2, 3) # EENTER, ERESUME
if enclave_mode == entry:
fault(GP, 0) # those enter an enclave from
# outside, the others run inside
leaf_function(eax) # each with its own checks, and
# flags as its page says
# with CET's indirect branch tracking waiting for an ENDBRANCH, any
# leaf but ERESUME first raises #CPRun on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no SGX, and every one raised an exception.
Operands
| Operand | Kind | Action |
|---|---|---|
ENCLU | ||
EAX | implicit | read |
RBX | implicit | conditional read, write |
RCX | implicit | conditional read, write |
RDX | implicit | conditional read, write |
Flags
None: XED records no flag that the forms test or change.
Leaf functions
ENCLU performs the leaf function whose number is in EAX; each has a page of its own. Only applications (CPL 3) may run ENCLU. Intel's SGX SDK gives all ten numbers, Open Enclave the first eight. Intel's future-extensions reference (319433-062) adds EREPORT2 and EGETKEY256, for 256-bit keys, which the manual does not document yet.
| EAX | Leaf function | Summary | Requires |
|---|---|---|---|
00H | EREPORT | Creates a report of the running enclave that a target enclave on the same platform can verify, for local attestation. | SGX1 |
01H | EGETKEY | Returns a 128-bit key from the processor's key hierarchy, such as a sealing key, as a KEYREQUEST structure asks. | SGX1 |
02H | EENTER | Enters an enclave through one of its thread control structures (TCS), at the entry point that the TCS gives. | SGX1 |
03H | ERESUME | Re-enters an enclave that an exception or interrupt left, with the state saved in its SSA frame. | SGX1 |
04H | EEXIT | Leaves the running enclave and continues at the address in RBX, outside it. | SGX1 |
05H | EACCEPT | Lets a running enclave accept a change that system software made to one of its pages with EAUG, EMODT or EMODPR. | SGX2 |
06H | EMODPE | Extends the access rights of a page of the running enclave, which the enclave may do by itself. | SGX2 |
07H | EACCEPTCOPY | Initializes a page that EAUG added by copying another page of the enclave into it, and accepts it. | SGX2 |
08H | EVERIFYREPORT2 | Checks, inside an enclave, the MAC of a report that a TDX trust domain created with SEAMREPORT. | EVERIFYREPORT2 |
09H | EDECCSSA | Decrements the index of the current SSA frame (TCS.CSSA) of the enclave thread, from inside the enclave. | EDECCSSA |
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
SGX | SGX | Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont Plus |
More SGX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026): Volume 3D, page 41-10 (ENCLU)
- Intel SGX SDK 2.25: common/inc/internal/inst.h (ENCLU and ENCLS leaf numbers, BSD license)
- Open Enclave SDK: include/openenclave/bits/sgx/sgxtypes.h (ENCLU leaf numbers, MIT license)
- Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.