ENCLV instruction (SGX)

Intel’s manual of September 2026 (325384-093) no longer documents ENCLV, and Intel’s future-extensions reference removed it in its June 2025 edition (319433-058, as the revision history of 319433-062 says). XED still decodes 0F 01 C0 as ENCLV, with an ISA set of its own, SGX_ENCLV, which its chip model gives to Tiger Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids and Diamond Rapids. No current Intel document and no openly licensed code that we could find gives its leaf functions, so unlike ENCLS and ENCLU it has no leaf pages here.

Forms

Every encoding of ENCLV that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ENCLV` ENCLV	`NP 0F 01 C0`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`ENCLV`
Ice Lake, Sapphire Rapids	100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

oss = cpuid_leaf(0x12, 0)[0] >> 5 & 1
if in_smm or not oss:
    fault(UD)                    # no SGX oversubscription
if not in_vmx:
    fault(UD)
if CPL > 0:
    fault(UD)                    # #UD, not #GP
if vmx_nonroot:
    p = current_vmcs
    pri = vmcs_read(p, 0x4002)   # processor-based controls; bit
    sec = 0                      # 31 activates the secondary ones
    if pri >> 31:
        sec = vmcs_read(p, 0x401E)
    if not sec >> 28 & 1:
        fault(UD)                # ENCLV not enabled in the guest
    bm = vmcs_read(p, 0x2036)    # the ENCLV-exiting bitmap
    if bm >> min(eax, 63) & 1:
        vm_exit(UNDEFINED)       # its basic exit reason unlisted
fc = msr[IA32_FEATURE_CONTROL]
if not fc & 1 or not fc >> 18 & 1:
    fault(GP, 0)                 # SGX not enabled: lock, bit 18
if not leaf_exists(eax):
    fault(GP, 0)
if not cr0 >> 31 & 1:
    fault(GP, 0)                 # paging off
leaf_function(eax)               # EDECVIRTCHILD (0), EINCVIRTCHILD
                                 # (1), ESETCONTEXT (2)
# written from revision 074 of Intel's SDM Volume 3 (April 2021),
# 40-14; revision 093 no longer documents ENCLV

Run on AMD Zen 5 (EPYC 9645): 2 cases. Every one raised an exception, at CPL 3, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ENCLV`
`EAX`	implicit	read
`RBX`	implicit	conditional read, write
`RCX`	implicit	conditional read, write
`RDX`	implicit	conditional read, write

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SGX_ENCLV` SGX	No CPUID bit in Intel's current manuals, which no longer document ENCLV; XED gives the instruction no requirement of its own.	Tiger Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

ENCLV