x86-64.net

Instruction

ENQCMD

Sends a 64-byte command, tagged with the PASID from the IA32_PASID MSR, to a device's enqueue register and sets ZF if the device did not accept it.

Extensions
Forms
2 (1 Legacy, 1 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of ENQCMD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
ENQCMD r16/32/64, m512 ENQCMD_GPRa_MEMu32F2 0F 38 F8 /rENQCMD
ENQCMD r16/32/64, m512 ENQCMD_GPRav_MEMu32_APXEVEX.LLZ.F2.MAP4.SCALABLE F8 /rAPX_F + ENQCMD

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
ENQCMD

ENQCMD
CPUID.(EAX=07H,ECX=0):ECX[29] ENQCMD

Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest
APX_F_ENQCMD

APX_F + ENQCMD
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):ECX[29] ENQCMD

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.