ENTER instruction (General-purpose)

ENTER builds a stack frame in one instruction: it pushes RBP, points RBP at the saved copy, and moves RSP down by the size in its first operand, the space for local variables. enter N, 0 therefore does the work of the usual prologue, push rbp, mov rbp, rsp, sub rsp, N, and LEAVE undoes it. The size is a 16-bit immediate, so one ENTER reserves at most 65,535 bytes.

The nesting level

The second operand serves languages with nested procedures, such as Pascal, in which an inner procedure reads the local variables of the ones around it. Before reserving the locals, ENTER copies the frame pointers of the enclosing levels from the old frame (level minus one of them) and then pushes the new frame’s own, building a table, the display, through which the procedure reaches each outer frame (Intel’s Volume 1, Chapter 6). Only the low five bits of the level count, as both manuals say: on Zen 5, levels 20h and 42h acted as 0 and 2.

Not in compiled code

Neither GCC 14 nor Clang 23 emits ENTER, at -O2 or with -fno-omit-frame-pointer; they write the prologue out. Intel’s optimization manual advises against ENTER for its many micro-ops and warns that a non-zero operand can stall the pipeline (Assembly/Compiler Coding Rules 28 and 29), and AMD’s Zen 5 guide lists it as microcoded.

Points to watch

The locals are not touched. ENTER writes the pushed slots only, but it faults as if it stored at the final RSP: AMD’s manual describes a write check there. A large frame thus probes one page, the lowest, and none between, unlike the loop that GCC and Clang insert with -fstack-clash-protection, which touches every 4 KiB on the way down.
Operand size. In 64-bit mode ENTER is 64-bit by default; a 66 prefix makes the pushes 2 bytes each, and 32 bits cannot be encoded. The 16-bit form writes only BP, keeping bits 63:16 of RBP, while RSP moves as a whole, as Zen 5 recorded. Intel’s pseudocode for 64-bit mode assigns all of RBP, but its text expects the upper bits to survive: it asks that RBP start within 16 KiB of RSP and that a 16-bit LEAVE end the frame.
No flags change.

Forms

Every encoding of ENTER that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ENTER imm16, imm8` ENTER_IMMw_IMMb	`C8 iw ib`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`imm16, imm8`
Sandy Bridge	100 / 0.33p015
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	100 / 0.25p0156
Alder Lake, Sapphire Rapids	126 / 11.5p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10
Lunar Lake	126 / 7.67p0 p1 p2 p3 p4 p5 p10 p11 p20 p21 p22 p25 p26 p27
Bonnell	32 / 16p01
Silvermont	100 / 1FPC0
Piledriver	100 / 0.5EX0 EX1
Zen, Zen 2	100 / 0.25
Zen 3, Zen 4	100 / 25ALU0 ALU1 ALU2 ALU3
Jaguar	100 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

nest = level & 31                # the nesting level, modulo 32
n = OSIZE // 8                   # 8 bytes; 2 with a 66 prefix
a = rsp - n
store(a, OSIZE, rBP)             # push rBP
frame = a
if nest > 0:
    for i in range(1, nest):     # the frame pointers of the enclosing
        a -= n                   # levels, from the old frame
        v = load(rbp - i * n, OSIZE)
        store(a, OSIZE, v)
    a -= n
    store(a, OSIZE, frame)       # and the new frame's own
if not writable(a - size):
    fault(PF)                    # a write at the new RSP would fault;
                                 # what was pushed stays in memory
rBP = frame                      # BP alone with a 66 prefix
rsp = a - size                   # the frame's size bytes, not written

Run on AMD Zen 5 (EPYC 9645): 23 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ENTER imm16, imm8`
`imm16`	explicit	read
`imm8`	explicit	read
`stack`	implicit	write
`rSP`	implicit	read, write
`rBP`	implicit	read, write

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I186` General-purpose	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

The nesting level#

Not in compiled code#

Points to watch#