Instruction
ENCLS with EAX = 0AH
Leaf CPUID
SGX1
CPUID.(EAX=12H,ECX=0):EAX[0]
Encoding
NP 0F 01 CF
Extensions
Data
Intel XED v2026.08.23

Leaf functions of ENCLS

ENCLS performs the leaf function whose number is in EAX. Only the operating system (CPL 0) may run ENCLS. The Linux kernel's headers give every number but ELDB's, which Linux does not use, and Intel's SGX SDK the first seven; ELDB's number is the one the manual gives.

EAXLeaf functionSummaryRequires
00HECREATEStarts building an enclave by copying its control structure, the SECS, from ordinary memory into a page of the EPC.SGX1
01HEADDCopies a page from ordinary memory into the EPC for an enclave being built, and adds its offset and attributes to the enclave's measurement.SGX1
02HEINITCompletes the build of an enclave: checks its signed SIGSTRUCT and launch token, fixes its measurement and makes it ready for EENTER.SGX1
03HEREMOVERemoves a page from the EPC, detaching it from its enclave and marking it unused.SGX1
04HEDBGRDReads eight bytes (four outside 64-bit mode) of a debug enclave's memory, at the address in RCX, into RBX.SGX1
05HEDBGWRWrites RBX (EBX outside 64-bit mode) to a debug enclave's memory at the address in RCX.SGX1
06HEEXTENDAdds 256 bytes of a page of an enclave being built to the enclave's measurement, MRENCLAVE.SGX1
07HELDBLoads a page that EWB wrote out back into the EPC, checking and decrypting it, and marks it blocked.SGX1
08HELDULoads a page that EWB wrote out back into the EPC, checking and decrypting it, and leaves it unblocked.SGX1
09HEBLOCKMarks an EPC page as blocked, the first step of evicting it from the EPC.SGX1
0AHEPATurns an EPC page into a version array, which holds the versions of pages evicted from the EPC.SGX1
0BHEWBEvicts a blocked EPC page: encrypts it, writes it to ordinary memory and keeps its version in a version array.SGX1
0CHETRACKStarts tracking the TLB flushes that must follow EBLOCK before the blocked pages of an enclave can be evicted.SGX1
0DHEAUGAdds a zeroed page to an enclave that is already running; the enclave must accept it with EACCEPT or EACCEPTCOPY.SGX2
0EHEMODPRRestricts the access rights of a page of a running enclave, which then accepts the change with EACCEPT.SGX2
0FHEMODTChanges the type of a page of a running enclave, to trim it for example, which then accepts the change with EACCEPT.SGX2
18HEUPDATESVNUpdates the SGX security version of the processor to that of the loaded microcode update, when the EPC holds no valid page.EUPDATESVN

CPUID and processors

EPA needs what ENCLS needs: the processor must report one of the alternatives of its ISA set, and the SGX1 bit, CPUID.(EAX=12H,ECX=0):EAX[0], as well.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Linux 7.3: arch/x86/include/asm/sgx.h (ENCLS leaf numbers)
  3. Intel SGX SDK 2.25: common/inc/internal/inst.h (ENCLU and ENCLS leaf numbers, BSD license)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026): Volume 3D, page 41-60 (EPA)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.