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Instruction

ERETS

Returns from a FRED event handler to code that also runs in ring 0, restoring the interrupted context from the stack.

Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of ERETS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
ERETS 64-bit mode only ERETSF2 0F 01 CAFRED

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
FRED

FRED
CPUID.(EAX=07H,ECX=1):EAX[17] FRED

Panther Lake, Nova Lake, Diamond Rapids

More FRED instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Flexible Return and Event Delivery (FRED) Specification (346446-009)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.