x86-64.net

ACE

ACE-E2 exception class

ACE-E2 is the ACE specification's exception class for BSRMOVF, which loads the whole block scale register: the ACE enabling checks, a loaded tile configuration, bsr0 as the only destination, #NM from CR0.TS or extended feature disable, and the faults of an optional memory source.

Class
ACE-E2 in Intel XED
Applies to
BSRMOVF (ACE), with its second source in a ZMM register or in memory.
Instructions
1 mnemonic, 2 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the ACE instructions exist only in 64-bit mode (IA32_EFER.LMA = 1 and CS.L = 1).
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCR4.OSXSAVE is 0, or XCR0 bits 17, 18 and 20 (the tile configuration, the tile data and ACE’s block scale state) are not all set.
#UDXCR0 bits 5 to 7 (the AVX-512 state) or bits 1 and 2 (the SSE and AVX state) are not all set.
#UDNo tile configuration is loaded.
#UDEVEX.z or EVEX.b is 1, EVEX.aaa is not 000B, or EVEX.L’L is not 10B: no masking or broadcast, and only 512-bit vectors.
#UDThe destination is not bsr0: ModRM.reg is not 000B, or EVEX.R or EVEX.R’ is 0.
#NMCR0.TS is 1.
#NMIA32_XFD bit 18 is set: extended feature disable blocks the tile data for this thread.
#SS(0)The memory address uses the SS segment and is not canonical.
#GPThe memory address is not canonical.
#PF(fault-code)Reading the memory source causes a page fault.
#AC(0)On processors whose alignment checking also tests 16-byte alignment of 16-, 32- and 64-byte accesses: the memory source is not 16-byte aligned while CR0.AM and EFLAGS.AC are 1 at CPL 3.

Notes

BSRMOVF takes the upper 512 bits of the 1024-bit block scale register from its first source and the lower 512 bits from the second. ModRM.reg names the block scale register, and bsr0 is the only one, so any other number, including one extended by EVEX.R or EVEX.R’, raises #UD. EVEX.vvvv and EVEX.V’ carry the first source, so this class has no check on them.

The #AC row depends on the implementation: the ACE specification allows processors to extend alignment checking to 16-byte alignment for these larger accesses.

  • ACE-E3: ACE-E3 is the ACE specification's exception class for BSRMOVH and BSRMOVL, which move one half of the block scale register to or from a ZMM register or memory: the checks of ACE-E2 plus an unused EVEX.vvvv.
  • ACE-E5: ACE-E5 is the ACE specification's exception class for BSRINIT, which resets the block scale register: the tile and block scale enabling checks, a loaded tile configuration, bsr0 as the only operand, and #NM when extended feature disable blocks the tile data.

Instructions

Intel XED puts forms of 1 mnemonic in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

ACE

Sources

  1. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026): Section 5.7.2; Section 5.8; Section 13.2.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.