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ACE

ACE-E4 exception class

ACE-E4 is the ACE specification's exception class for the outer products, which accumulate the outer product of two ZMM registers into a tile: the ACE and AVX-512 enabling checks, a configured and valid tile, fixed EVEX fields, and #NM from CR0.TS or extended feature disable.

Class
ACE-E4 in Intel XED
Applies to
The outer products of ACE: TOP4BSSD, TOP4BSUD, TOP4BUSD and TOP4BUUD, TOP2BF16PS, and the microscaling forms TOP4MXBF8PS, TOP4MXBHF8PS, TOP4MXHBF8PS, TOP4MXHF8PS and TOP4MXBSSPS.
Instructions
10 mnemonics, 10 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the ACE instructions exist only in 64-bit mode (IA32_EFER.LMA = 1 and CS.L = 1).
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCR4.OSXSAVE is 0, or XCR0 bits 17, 18 and 20 (the tile configuration, the tile data and ACE’s block scale state) are not all set.
#UDXCR0 bits 5 to 7 (the AVX-512 state) or bits 1 and 2 (the SSE and AVX state) are not all set.
#UDNo tile configuration is loaded, or the destination is not a valid tile of the current palette.
#UDEVEX.z or EVEX.b is 1, EVEX.aaa is not 000B, or EVEX.L’L is not 10B: no masking or broadcast, and only 512-bit vectors.
#NMCR0.TS is 1.
#NMIA32_XFD bit 18 is set: extended feature disable blocks the tile data for this thread.

Notes

The outer products read two ZMM registers, one of them through EVEX.vvvv, and write only a tile, so there are no memory faults and no check on vvvv. Unlike the AMX dot products (AMX-E4), the class has no conditions on tile shapes. The MX forms also read the block scale register, whose groups the immediate selects; see TOP4BSSD for the basic operation.

  • AMX-E4: AMX-E4 is the class that Intel's table of AMX exception classes gives the tile matrix multiplications: the shared AMX checks, three distinct and valid tiles whose shapes fit a multiplication within the matrix unit's limits, and #NM when extended feature disable blocks the tile data.
  • ACE-E2: ACE-E2 is the ACE specification's exception class for BSRMOVF, which loads the whole block scale register: the ACE enabling checks, a loaded tile configuration, bsr0 as the only destination, #NM from CR0.TS or extended feature disable, and the faults of an optional memory source.

Instructions

Intel XED puts forms of 10 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

ACE

Sources

  1. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026): Section 5.7.4; Chapter 14.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.