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ACE

ACE-E5 exception class

ACE-E5 is the ACE specification's exception class for BSRINIT, which resets the block scale register: the tile and block scale enabling checks, a loaded tile configuration, bsr0 as the only operand, and #NM when extended feature disable blocks the tile data.

Class
ACE-E5 in Intel XED
Applies to
BSRINIT (ACE), which is VEX-encoded.
Instructions
1 mnemonic, 1 form
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the ACE instructions exist only in 64-bit mode (IA32_EFER.LMA = 1 and CS.L = 1).
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the VEX prefix.
#UDCR4.OSXSAVE is 0, or XCR0 bits 17, 18 and 20 (the tile configuration, the tile data and ACE’s block scale state) are not all set.
#UDVEX.vvvv is not 1111B.
#UDNo tile configuration is loaded.
#UDModRM.reg is not 000B: bsr0 is the only block scale register.
#NMIA32_XFD bit 18 is set: extended feature disable blocks the tile data for this thread.

Notes

BSRINIT sets every byte of the block scale register to 7FH, a scale of 1.0. It touches no vector register, so, unlike the other ACE classes, ACE-E5 checks neither the AVX-512 nor the SSE and AVX bits of XCR0, and it has no #NM for CR0.TS.

  • ACE-E2: ACE-E2 is the ACE specification's exception class for BSRMOVF, which loads the whole block scale register: the ACE enabling checks, a loaded tile configuration, bsr0 as the only destination, #NM from CR0.TS or extended feature disable, and the faults of an optional memory source.
  • ACE-E3: ACE-E3 is the ACE specification's exception class for BSRMOVH and BSRMOVL, which move one half of the block scale register to or from a ZMM register or memory: the checks of ACE-E2 plus an unused EVEX.vvvv.

Instructions

Intel XED puts forms of 1 mnemonic in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

ACE

Sources

  1. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026): Section 5.7.5 and its footnote; Section 13.1.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.