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ACE

ACE-E6 exception class

ACE-E6 is the ACE specification's exception class for its tile moves with the row or column number in a general-purpose register: the checks of ACE-E1, except that EVEX.vvvv names that register.

Class
ACE-E6 in Intel XED
Applies to
The register forms of TILEMOVROW and TILEMOVCOL that write a ZMM register into a row or column of a tile (ACE).
Instructions
2 mnemonics, 2 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the ACE instructions exist only in 64-bit mode (IA32_EFER.LMA = 1 and CS.L = 1).
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCR4.OSXSAVE is 0, or XCR0 bits 17, 18 and 20 (the tile configuration, the tile data and ACE’s block scale state) are not all set.
#UDXCR0 bits 5 to 7 (the AVX-512 state) or bits 1 and 2 (the SSE and AVX state) are not all set.
#UDNo tile configuration is loaded, or the tile operand is not a valid tile of the current palette.
#UDEVEX.z or EVEX.b is 1, EVEX.aaa is not 000B, or EVEX.L’L is not 10B: no masking or broadcast, and only 512-bit vectors.
#UDEVEX.U is 0.
#UDEVEX.V’ is 0.
#NMCR0.TS is 1.
#NMIA32_XFD bit 18 is set: extended feature disable blocks the tile data for this thread.

Notes

EVEX.vvvv names the 32-bit register whose low 4 bits select the row or column; a larger value does not fault. The ACE specification split this class from ACE-E1 in its revision 1.12, and it applies the pair to the tile-to-ZMM forms of TILEMOVROW and to the TCVTROW conversions as well, where XED keeps AMX-E8-EVEX.

  • ACE-E1: ACE-E1 is the ACE specification's exception class for its tile moves with an immediate row or column number: the AMX, ACE and AVX-512 enabling checks, a configured and valid tile, fixed EVEX fields, and #NM from CR0.TS or extended feature disable.
  • AMX-E8-EVEX: AMX-E8-EVEX is the ISE's AMX exception class for the AMX-AVX512 instructions that move a tile row, selected by a general-purpose register, into a ZMM register: the checks of AMX-E7-EVEX, except that EVEX.vvvv names that register.

Instructions

Intel XED puts forms of 2 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

ACE

Sources

  1. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026): Section 5.7.6; Revision History (1.12); Chapter 12.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.