x86-64.net

AMX

AMX-E1 exception class

AMX-E1 is the class that Intel's table of AMX exception classes gives LDTILECFG: the invalid-opcode checks shared by all AMX instructions, a general-protection fault for a tile configuration the processor rejects, and the faults of reading the 64-byte configuration from memory.

Class
AMX-E1 in Intel XED
Applies to
LDTILECFG in its VEX encoding (AMX-TILE). Its EVEX encoding, added by APX, has AMX-E1-EVEX.
Instructions
1 mnemonic, 1 form
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: AMX instructions exist only in 64-bit mode (IA32_EFER.LMA = 1 and CS.L = 1).
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the VEX prefix.
#UDCR4.OSXSAVE is 0, or XCR0 bits 17 (TILECFG) and 18 (TILEDATA) are not both set: the operating system has not enabled the AMX state.
#UDVEX.vvvv is not 1111B.
#GPThe configuration fails LDTILECFG’s checks: a palette above the highest one supported or one that XCR0 does not cover, a nonzero reserved byte, a tile with more rows or more bytes per row than the palette allows, or a tile with only one of those two values zero.
#GPThe memory address is not canonical.
#SS(0)The memory address uses the SS segment and is not canonical.
#PF(fault-code)Reading the configuration causes a page fault.

Notes

AMX-E1 has no #NM row. Extended feature disable (XFD) lets an operating system enable AMX but keep the 8 KiB of tile data from threads that have not asked for it, and those threads get #NM from tile instructions. LDTILECFG is an exception: it runs even while IA32_XFD bit 18 is set, because it puts the tile data in its initial state instead of using it.

The #GP checks are spelled out in LDTILECFG’s pseudocode. Palette 0 is valid and returns the tiles to their unconfigured state. AMX instructions never raise #AC, so alignment checking does not apply to the 64-byte block.

  • AMX-E1-EVEX: AMX-E1-EVEX is the ISE's and the APX specification's class for LDTILECFG in its EVEX encoding: all of AMX-E1, plus invalid-opcode checks on the EVEX fields that the instruction leaves unused.
  • AMX-E2: AMX-E2 is the class that Intel's table of AMX exception classes gives STTILECFG: the invalid-opcode checks shared by all AMX instructions and the faults of writing the 64-byte configuration to memory.

Instructions

Intel XED puts forms of 1 mnemonic in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AMX-TILE

ACE

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.10, Table 2-67; LDTILECFG, Operation.
  2. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026): Section 3.6, Table 3-2.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026): Section 13.14.
  4. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026): Section 5.6.1.
  5. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.