x86-64.net

AMX

AMX-E2-EVEX exception class

AMX-E2-EVEX is the ISE's and the APX specification's class for STTILECFG in its EVEX encoding: all of AMX-E2, plus invalid-opcode checks on the EVEX fields that the instruction leaves unused.

Class
AMX-E2-EVEX in Intel XED
Applies to
STTILECFG in the EVEX encoding of APX, whose address can use the registers R16 to R31.
Instructions
1 mnemonic, 1 form
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: AMX instructions exist only in 64-bit mode.
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCR4.OSXSAVE is 0, or XCR0 bits 17 and 18 are not both set.
#UDMasking, broadcast or a vector length is encoded: EVEX.z or EVEX.b is 1, EVEX.aaa is not 000B, or EVEX.L’L is not 00B.
#UDEVEX.vvvv is not 1111B or EVEX.V’ is not 1: the instruction has no register operand there.
#GPThe memory address is not canonical.
#SS(0)The memory address uses the SS segment and is not canonical.
#PF(fault-code)Writing the configuration causes a page fault.

Notes

As with the other VEX instructions that APX promotes to EVEX, the encoding exists for the new general-purpose registers R16 to R31, and it raises #UD while XCR0 bit 19 (APX) is 0, a rule of the APX specification that the class tables do not repeat.

  • AMX-E2: AMX-E2 is the class that Intel's table of AMX exception classes gives STTILECFG: the invalid-opcode checks shared by all AMX instructions and the faults of writing the 64-byte configuration to memory.
  • AMX-E1-EVEX: AMX-E1-EVEX is the ISE's and the APX specification's class for LDTILECFG in its EVEX encoding: all of AMX-E1, plus invalid-opcode checks on the EVEX fields that the instruction leaves unused.

Instructions

Intel XED puts forms of 1 mnemonic in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

APX

Sources

  1. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026): Section 3.6, Table 3-2.
  2. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025): Section 4.2.2, Table 4.3; Section 3.1.2.3; Section 3.1.4.2.1, Table 3.8.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.