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AMX

AMX-E3-EVEX exception class

AMX-E3-EVEX is the ISE's and the APX specification's class for the tile loads and stores in their EVEX encoding: all of AMX-E3, plus invalid-opcode checks on the EVEX fields they leave unused.

Class
AMX-E3-EVEX in Intel XED
Applies to
The EVEX encodings of TILELOADD, TILELOADDT1 and TILESTORED and of TILELOADDRS and TILELOADDRST1, added by APX so that the base and index registers can be R16 to R31.
Instructions
5 mnemonics, 5 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: AMX instructions exist only in 64-bit mode.
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCR4.OSXSAVE is 0, or XCR0 bits 17 and 18 are not both set.
#UDMasking, broadcast or a vector length is encoded: EVEX.z or EVEX.b is 1, EVEX.aaa is not 000B, or EVEX.L’L is not 00B.
#UDEVEX.vvvv is not 1111B or EVEX.V’ is not 1: the instruction has no register operand there.
#UDThe memory operand has no SIB byte, which holds the row stride in its index register.
#UDNo tile configuration is loaded, or the tile operand is not a valid tile of the current palette.
#UDThe tile’s bytes per row are not a multiple of 4, or TILECFG.start_row is not below the tile’s number of rows.
#NMIA32_XFD bit 18 is set: extended feature disable blocks the tile data for this thread.
#SS(0)A row’s address uses the SS segment and is not canonical.
#GPA row’s address is not canonical.
#PF(fault-code)Accessing a row causes a page fault.

Notes

Besides the checks listed, the EVEX forms raise #UD while XCR0 bit 19 (APX) is 0, because the APX specification counts every VEX instruction promoted to EVEX as an APX instruction.

  • AMX-E3: AMX-E3 is the class that Intel's table of AMX exception classes gives the tile loads and stores: the shared AMX checks, a configured and valid tile, SIB addressing, the faults of the memory rows and #NM when extended feature disable blocks the tile data.
  • AMX-E1-EVEX: AMX-E1-EVEX is the ISE's and the APX specification's class for LDTILECFG in its EVEX encoding: all of AMX-E1, plus invalid-opcode checks on the EVEX fields that the instruction leaves unused.

Instructions

Intel XED puts forms of 5 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

APX

Sources

  1. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026): Section 3.6, Table 3-2; TILELOADDRS[,T1], Exceptions.
  2. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025): Section 4.2.3, Table 4.4; Section 3.1.4.2.1, Table 3.8.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.