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AMX

AMX-E3 exception class

AMX-E3 is the class that Intel's table of AMX exception classes gives the tile loads and stores: the shared AMX checks, a configured and valid tile, SIB addressing, the faults of the memory rows and #NM when extended feature disable blocks the tile data.

Class
AMX-E3 in Intel XED
Applies to
The VEX encodings of TILELOADD, TILELOADDT1 and TILESTORED (AMX-TILE) and of TILELOADDRS and TILELOADDRST1 (AMX-MOVRS). Their EVEX encodings have AMX-E3-EVEX.
Instructions
5 mnemonics, 5 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: AMX instructions exist only in 64-bit mode (IA32_EFER.LMA = 1 and CS.L = 1).
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the VEX prefix.
#UDCR4.OSXSAVE is 0, or XCR0 bits 17 (TILECFG) and 18 (TILEDATA) are not both set: the operating system has not enabled the AMX state.
#UDVEX.vvvv is not 1111B.
#UDThe memory operand has no SIB byte. The index register of the SIB address gives the distance between rows, so it is required.
#UDNo tile configuration is loaded, or the tile operand is not a valid tile of the current palette: not configured, or numbered at or above the palette’s number of tiles.
#UDThe tile’s bytes per row are not a multiple of 4, or TILECFG.start_row is not below the tile’s number of rows.
#NMIA32_XFD bit 18 is set: extended feature disable blocks the tile data for this thread.
#SS(0)A row’s address uses the SS segment and is not canonical.
#GPA row’s address is not canonical.
#PF(fault-code)Accessing a row causes a page fault.

Notes

A tile load or store touches one memory row per tile row, and a page fault can stop it halfway. TILECFG.start_row then holds the first row not yet done, and executing the instruction again continues from there, which is why a start_row beyond the tile’s last row is an error.

The #NM comes from extended feature disable (XFD), with which an operating system keeps the tile data from threads that have not asked for it. On Linux, a program asks with arch_prctl(ARCH_REQ_XCOMP_PERM, 18), and a tile instruction used without that permission raises SIGILL. AMX instructions never raise #AC, so unaligned rows do not fault.

  • AMX-E3-EVEX: AMX-E3-EVEX is the ISE's and the APX specification's class for the tile loads and stores in their EVEX encoding: all of AMX-E3, plus invalid-opcode checks on the EVEX fields they leave unused.
  • AMX-E4: AMX-E4 is the class that Intel's table of AMX exception classes gives the tile matrix multiplications: the shared AMX checks, three distinct and valid tiles whose shapes fit a multiplication within the matrix unit's limits, and #NM when extended feature disable blocks the tile data.

Instructions

Intel XED puts forms of 5 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AMX-TILE

AMX-MOVRS

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.10, Table 2-67.
  2. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026): Section 3.6, Table 3-2; TILELOADDRS[,T1], Exceptions.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026): Section 13.14; Section 19.1.4.
  4. Linux kernel documentation: Using XSTATE features in user space applications: Permission requests with arch_prctl(ARCH_REQ_XCOMP_PERM).
  5. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.