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AMX

AMX-E4 exception class

AMX-E4 is the class that Intel's table of AMX exception classes gives the tile matrix multiplications: the shared AMX checks, three distinct and valid tiles whose shapes fit a multiplication within the matrix unit's limits, and #NM when extended feature disable blocks the tile data.

Class
AMX-E4 in Intel XED
Applies to
The tile multiplications: the AMX-INT8 dot products (TDPBSSD, TDPBSUD, TDPBUSD, TDPBUUD), TDPBF16PS (AMX-BF16), TDPFP16PS (AMX-FP16), TCMMIMFP16PS and TCMMRLFP16PS (AMX-COMPLEX) and the FP8 dot products of AMX-FP8 (TDPBF8PS, TDPBHF8PS, TDPHBF8PS, TDPHF8PS).
Instructions
12 mnemonics, 12 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: AMX instructions exist only in 64-bit mode (IA32_EFER.LMA = 1 and CS.L = 1).
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the VEX prefix.
#UDCR4.OSXSAVE is 0, or XCR0 bits 17 (TILECFG) and 18 (TILEDATA) are not both set: the operating system has not enabled the AMX state.
#UDTwo of the three tile operands are the same register.
#UDNo tile configuration is loaded, or a tile operand is not a valid tile of the current palette.
#UDThe bytes per row of one of the three tiles are not a multiple of 4.
#UDThe shapes do not fit a matrix multiplication: the accumulator and the second source differ in bytes per row, the accumulator and the first source differ in rows, or the first source’s bytes per row divided by 4 differ from the second source’s rows.
#UDA shape exceeds the matrix unit: more than tmul_maxn bytes per row in the accumulator or the second source, or more than tmul_maxk in the first source’s bytes per row divided by 4 or in the second source’s rows.
#NMIA32_XFD bit 18 is set: extended feature disable blocks the tile data for this thread.

Notes

The multiplications have no memory operand, so there are no memory faults, and VEX.vvvv is not checked because it names the second source tile. All three tiles are processed a dword at a time (a source dword holds two or four narrow elements), so every row length must be a multiple of 4. CPUID leaf 1EH reports the limits of the matrix unit; the SDM gives 16 for tmul_maxk and 64 for tmul_maxn, which match the 16 rows of 64 bytes of a palette 1 tile.

The FP8 dot products of AMX-FP8 are in the ISE, the others in SDM Volume 2; both use this class. See TDPBSSD for how the three tiles relate.

  • AMX-E3: AMX-E3 is the class that Intel's table of AMX exception classes gives the tile loads and stores: the shared AMX checks, a configured and valid tile, SIB addressing, the faults of the memory rows and #NM when extended feature disable blocks the tile data.
  • AMX-E5: AMX-E5 is the class that Intel's table of AMX exception classes gives TILEZERO: the shared AMX checks, a configured and valid destination tile, and #NM when extended feature disable blocks the tile data.

Instructions

Intel XED puts forms of 12 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AMX-INT8

AMX-BF16

AMX-FP16

AMX-COMPLEX

AMX-FP8

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.10, Table 2-67; TDPBSSD/TDPBSUD/TDPBUSD/TDPBUUD.
  2. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026): Section 3.6, Table 3-2; TDP[B,H,BH,HB]F8PS, Exceptions.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026): Section 21.3, Tables 21-68 and 21-69 (CPUID leaves 1DH and 1EH).
  4. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.