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AMX

AMX-E5 exception class

AMX-E5 is the class that Intel's table of AMX exception classes gives TILEZERO: the shared AMX checks, a configured and valid destination tile, and #NM when extended feature disable blocks the tile data.

Class
AMX-E5 in Intel XED
Applies to
TILEZERO (AMX-TILE).
Instructions
1 mnemonic, 1 form
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: AMX instructions exist only in 64-bit mode (IA32_EFER.LMA = 1 and CS.L = 1).
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the VEX prefix.
#UDCR4.OSXSAVE is 0, or XCR0 bits 17 (TILECFG) and 18 (TILEDATA) are not both set: the operating system has not enabled the AMX state.
#UDVEX.vvvv is not 1111B.
#UDNo tile configuration is loaded, or the destination is not a valid tile of the current palette: not configured, or numbered at or above the palette’s number of tiles.
#NMIA32_XFD bit 18 is set: extended feature disable blocks the tile data for this thread.

Notes

TILEZERO clears one configured tile, typically an accumulator before a new block of results. Unlike TILERELEASE, it needs a loaded configuration and counts as a use of the tile data, so extended feature disable (XFD) stops it with #NM. The ACE specification, whose second palette reuses this instruction, gives it the same class.

  • AMX-E6: AMX-E6 is the class that Intel's table of AMX exception classes gives TILERELEASE, which only makes the checks shared by all AMX instructions.
  • AMX-E4: AMX-E4 is the class that Intel's table of AMX exception classes gives the tile matrix multiplications: the shared AMX checks, three distinct and valid tiles whose shapes fit a multiplication within the matrix unit's limits, and #NM when extended feature disable blocks the tile data.

Instructions

Intel XED puts forms of 1 mnemonic in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AMX-TILE

ACE

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.10, Table 2-67.
  2. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026): Section 3.6, Table 3-2.
  3. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026): Section 5.6.3.
  4. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.