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AMX

AMX-E6 exception class

AMX-E6 is the class that Intel's table of AMX exception classes gives TILERELEASE, which only makes the checks shared by all AMX instructions.

Class
AMX-E6 in Intel XED
Applies to
TILERELEASE (AMX-TILE).
Instructions
1 mnemonic, 1 form
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: AMX instructions exist only in 64-bit mode (IA32_EFER.LMA = 1 and CS.L = 1).
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the VEX prefix.
#UDCR4.OSXSAVE is 0, or XCR0 bits 17 (TILECFG) and 18 (TILEDATA) are not both set: the operating system has not enabled the AMX state.
#UDVEX.vvvv is not 1111B.

Notes

TILERELEASE returns the configuration and all tile data to their initial state, so it works without a configuration, and extended feature disable (XFD) does not stop it: it initializes the tile data instead of using it. The SDM advises system software to release the tiles this way before it disables AMX, since tile state left in use can cost power and performance.

  • AMX-E5: AMX-E5 is the class that Intel's table of AMX exception classes gives TILEZERO: the shared AMX checks, a configured and valid destination tile, and #NM when extended feature disable blocks the tile data.
  • AMX-E1: AMX-E1 is the class that Intel's table of AMX exception classes gives LDTILECFG: the invalid-opcode checks shared by all AMX instructions, a general-protection fault for a tile configuration the processor rejects, and the faults of reading the 64-byte configuration from memory.

Instructions

Intel XED puts forms of 1 mnemonic in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AMX-TILE

ACE

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.10, Table 2-67.
  2. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026): Section 3.6, Table 3-2.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026): Section 13.14; Section 19.2.
  4. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026): Section 5.6.4.
  5. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.