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AMX

AMX-E7-EVEX exception class

AMX-E7-EVEX is the ISE's AMX exception class for the AMX-AVX512 instructions that move a tile row, selected by an immediate, into a ZMM register (converting it in the TCVTROW forms): the AMX and AVX-512 enabling checks, a configured source tile, fixed EVEX fields, and #NM from CR0.TS or extended feature disable.

Class
AMX-E7-EVEX in Intel XED
Applies to
The immediate forms of TILEMOVROW, TCVTROWD2PS, TCVTROWPS2BF16H, TCVTROWPS2BF16L, TCVTROWPS2PHH and TCVTROWPS2PHL (AMX-AVX512).
Instructions
6 mnemonics, 6 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: AMX instructions exist only in 64-bit mode (IA32_EFER.LMA = 1 and CS.L = 1).
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCR4.OSXSAVE is 0, or XCR0 does not enable all of the AMX state (bits 17 and 18), the AVX-512 state (bits 5 to 7) and the SSE and AVX state (bits 1 and 2).
#UDNo tile configuration is loaded, or the source is not a valid tile of the current palette.
#UDThe source tile’s bytes per row are not a multiple of 4.
#UDEVEX.z or EVEX.b is 1, EVEX.aaa is not 000B, or EVEX.L’L is not 10B: no masking or broadcast, and only 512-bit vectors.
#UDEVEX.U is 0.
#UDEVEX.vvvv is not 1111B or EVEX.V’ is not 1: the immediate, not vvvv, selects the row.
#NMCR0.TS is 1.
#NMIA32_XFD bit 18 is set: extended feature disable blocks the tile data for this thread.

Notes

These instructions connect AMX to AVX-512, so they need both register files enabled and also take the AVX-512 #NM for CR0.TS. A row number beyond the tile’s configured rows is not an error: the ZMM destination is zeroed.

The ISE’s page for TILEMOVROW names the two classes the other way round, AMX-E7-EVEX for the register form and AMX-E8-EVEX for the immediate form. The ISE’s pages of the TCVTROW conversions and XED give AMX-E7-EVEX to the immediate forms, and only those can meet the class’s demand for an unused vvvv. The ACE specification assigns its own classes, ACE-E1 and ACE-E6, to the same instructions.

  • AMX-E8-EVEX: AMX-E8-EVEX is the ISE's AMX exception class for the AMX-AVX512 instructions that move a tile row, selected by a general-purpose register, into a ZMM register: the checks of AMX-E7-EVEX, except that EVEX.vvvv names that register.
  • ACE-E1: ACE-E1 is the ACE specification's exception class for its tile moves with an immediate row or column number: the AMX, ACE and AVX-512 enabling checks, a configured and valid tile, fixed EVEX fields, and #NM from CR0.TS or extended feature disable.

Instructions

Intel XED puts forms of 6 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AMX-AVX512

ACE

Sources

  1. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026): Section 3.6, Table 3-2; TCVTROWD2PS and TILEMOVROW, Operation and Exceptions.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026): Sections 12.2 to 12.6.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.