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AMX

AMX-E8-EVEX exception class

AMX-E8-EVEX is the ISE's AMX exception class for the AMX-AVX512 instructions that move a tile row, selected by a general-purpose register, into a ZMM register: the checks of AMX-E7-EVEX, except that EVEX.vvvv names that register.

Class
AMX-E8-EVEX in Intel XED
Applies to
The register forms of TILEMOVROW, TCVTROWD2PS, TCVTROWPS2BF16H, TCVTROWPS2BF16L, TCVTROWPS2PHH and TCVTROWPS2PHL (AMX-AVX512).
Instructions
6 mnemonics, 6 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: AMX instructions exist only in 64-bit mode (IA32_EFER.LMA = 1 and CS.L = 1).
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCR4.OSXSAVE is 0, or XCR0 does not enable all of the AMX state (bits 17 and 18), the AVX-512 state (bits 5 to 7) and the SSE and AVX state (bits 1 and 2).
#UDNo tile configuration is loaded, or the source is not a valid tile of the current palette.
#UDThe source tile’s bytes per row are not a multiple of 4.
#UDEVEX.z or EVEX.b is 1, EVEX.aaa is not 000B, or EVEX.L’L is not 10B: no masking or broadcast, and only 512-bit vectors.
#UDEVEX.U is 0.
#UDEVEX.V’ is 0.
#NMCR0.TS is 1.
#NMIA32_XFD bit 18 is set: extended feature disable blocks the tile data for this thread.

Notes

EVEX.vvvv holds the 32-bit register with the row number, of which only the low 4 bits count; a row beyond the tile’s configured rows zeroes the destination instead of faulting. Otherwise the class matches AMX-E7-EVEX, including the swapped class names on the ISE’s TILEMOVROW page described there.

  • AMX-E7-EVEX: AMX-E7-EVEX is the ISE's AMX exception class for the AMX-AVX512 instructions that move a tile row, selected by an immediate, into a ZMM register (converting it in the TCVTROW forms): the AMX and AVX-512 enabling checks, a configured source tile, fixed EVEX fields, and #NM from CR0.TS or extended feature disable.
  • ACE-E6: ACE-E6 is the ACE specification's exception class for its tile moves with the row or column number in a general-purpose register: the checks of ACE-E1, except that EVEX.vvvv names that register.

Instructions

Intel XED puts forms of 6 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AMX-AVX512

ACE

Sources

  1. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026): Section 3.6, Table 3-2; TCVTROWD2PS and TILEMOVROW, Operation and Exceptions.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.