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APX

APX-EVEX-BMI exception class

APX-EVEX-BMI is the APX specification's exception class for the BMI1 and BMI2 instructions in their EVEX encoding, which APX adds so that they can use the registers R16 to R31 and, for some of them, leave the flags unchanged.

Class
APX-EVEX-BMI in Intel XED
Applies to
The EVEX encodings of ANDN, BEXTR, BLSI, BLSMSK, BLSR, BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX and SHRX, in maps 2 and 3 with the opcodes of their VEX forms.
Instructions
13 mnemonics, 76 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the EVEX prefix raises #UD in real-address and virtual-8086 mode.
#UDAlways: the EVEX forms of the BMI instructions exist only in 64-bit mode.
#UDXCR0 bit 19 (APX) or CR4.OSXSAVE is 0: the operating system has not enabled APX.
#UDA bit of the last EVEX payload byte other than V4, L and NF is 1, or EVEX.L is 1.
#UDEVEX.NF is 1 on an instruction that cannot suppress the flags: only ANDN, BEXTR, BLSI, BLSMSK, BLSR and BZHI can.
#UDThe operand is a register (ModRM.mod = 11B) and EVEX.U is 0.
#UDAny other invalid-opcode condition of the VEX form holds.
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCPUID reports no APX_F, or not the BMI1 or BMI2 feature the instruction belongs to.
#SS(0)The memory address uses the SS segment and is not canonical.
#GP(0)The memory address is not canonical.
#PF(fault-code)The memory access causes a page fault.
#AC(0)Alignment checking is enabled, CPL is 3 and the memory access is unaligned.

Notes

With a memory operand, EVEX.U supplies the top bit of the index register (inverted), so APX can address R16 to R31 there; with a register operand it has no use and must stay 1. NF = 1 makes the six flag-writing instructions leave the flags unchanged. Like the other promoted instructions that use only general-purpose registers, these ignore CR0.TS and never raise #NM.

For the other #UD conditions, the APX table points to Tables 2-37 and 2-39 of SDM Volume 2. In revision 093 of the SDM, the VEX forms of these instructions have exception type 13 (Section 2.6.1, Table 2-29).

  • APX-EVEX-INT: APX-EVEX-INT is the APX specification's exception class for the integer instructions that APX promotes from the legacy maps into EVEX map 4, for the registers R16 to R31, a new destination register (NDD), flag suppression (NF) and zero-upper forms (ZU).
  • APX-EVEX-CMPCCXADD: APX-EVEX-CMPCCXADD is the APX specification's exception class for CMPccXADD in its EVEX encoding, which APX adds so that the instruction can use the registers R16 to R31.

Instructions

Intel XED puts forms of 13 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

APX

Sources

  1. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025): Section 4.2.4, Table 4.5; Sections 3.1.2.3 and 3.1.2.3.2.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.6.1, Table 2-29.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.