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APX

APX-EVEX-CCMP exception class

APX-EVEX-CCMP is the APX specification's exception class for CCMPscc and CTESTscc, the conditional compare and test instructions that APX adds in EVEX map 4.

Class
APX-EVEX-CCMP in Intel XED
Applies to
CCMPscc and CTESTscc (APX), which reuse the opcodes of CMP and TEST in EVEX map 4.
Instructions
2 mnemonics, 20 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the EVEX prefix raises #UD in real-address and virtual-8086 mode.
#UDAlways: EVEX map 4, where these instructions are, exists only in 64-bit mode.
#UDXCR0 bit 19 (APX) or CR4.OSXSAVE is 0: the operating system has not enabled APX.
#UDA bit of the last EVEX payload byte other than the source condition bits SC3 to SC0 is 1.
#UDThe operand is a register (ModRM.mod = 11B) and EVEX.U is 0.
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCPUID reports no APX_F.
#SS(0)The memory address uses the SS segment and is not canonical.
#GP(0)The memory address is not canonical.
#PF(fault-code)The memory access causes a page fault.
#AC(0)Alignment checking is enabled, CPL is 3 and the memory access is unaligned.

Notes

When the source condition is false, CCMPscc and CTESTscc skip the comparison and set OF, SF, ZF and CF from the default flags value, which sits where EVEX.vvvv usually is (PF gets CF’s value and AF is cleared). Unlike CFCMOVcc, a false condition does not suppress the faults of a memory operand, so these rows apply whatever the condition.

  • APX-EVEX-CFCMOV: APX-EVEX-CFCMOV is the APX specification's exception class for CFCMOVcc, the conditionally faulting CMOVcc of EVEX map 4, whose memory faults and debug exceptions occur only when the condition is true.
  • APX-EVEX-INT: APX-EVEX-INT is the APX specification's exception class for the integer instructions that APX promotes from the legacy maps into EVEX map 4, for the registers R16 to R31, a new destination register (NDD), flag suppression (NF) and zero-upper forms (ZU).

Instructions

Intel XED puts forms of 2 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

APX

Sources

  1. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025): Section 4.2.5, Table 4.6; Section 3.1.3.2.1.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.