x86-64.net

APX

APX-EVEX-CFCMOV exception class

APX-EVEX-CFCMOV is the APX specification's exception class for CFCMOVcc, the conditionally faulting CMOVcc of EVEX map 4, whose memory faults and debug exceptions occur only when the condition is true.

Class
APX-EVEX-CFCMOV in Intel XED
Applies to
CFCMOVcc (APX) in its three forms, a load, a store and a form with a new destination register, all in EVEX map 4.
Instructions
1 mnemonic, 5 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the EVEX prefix raises #UD in real-address and virtual-8086 mode.
#UDAlways: EVEX map 4, where these instructions are, exists only in 64-bit mode.
#UDXCR0 bit 19 (APX) or CR4.OSXSAVE is 0: the operating system has not enabled APX.
#UDA bit of the last EVEX payload byte other than ND, V4 and NF is 1.
#UDEVEX.ND is 0 and EVEX.V4 and EVEX.vvvv are not all 1s.
#UDThe operand is a register (ModRM.mod = 11B) and EVEX.U is 0.
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCPUID reports no APX_F.
#SS(0)The condition is true, and the memory address uses the SS segment and is not canonical.
#GP(0)The condition is true and the memory address is not canonical.
#PF(fault-code)The condition is true and the memory access causes a page fault.
#AC(0)The condition is true, alignment checking is enabled, CPL is 3 and the memory access is unaligned.
#DBThe condition is true and the instruction triggers a debug exception.

Notes

With a false condition, CFCMOVcc suppresses every memory fault and #DB: the load form zeroes its destination register, the form with a new destination copies the other register source into it, and the store form writes nothing. The APX specification presents these instructions as a way for compilers to if-convert larger regions of code, since a guarded load or store no longer needs a branch. The EVEX CMOVcc with a new destination (ND = 1, NF = 0) does not suppress faults and belongs to APX-EVEX-INT; CMOVcc with a REX2 prefix behaves like the legacy instruction.

  • APX-EVEX-CCMP: APX-EVEX-CCMP is the APX specification's exception class for CCMPscc and CTESTscc, the conditional compare and test instructions that APX adds in EVEX map 4.
  • APX-EVEX-INT: APX-EVEX-INT is the APX specification's exception class for the integer instructions that APX promotes from the legacy maps into EVEX map 4, for the registers R16 to R31, a new destination register (NDD), flag suppression (NF) and zero-upper forms (ZU).

Instructions

Intel XED puts forms of 1 mnemonic in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

APX

Sources

  1. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025): Section 4.2.8, Table 4.9; Sections 3.1.3.2 and 3.1.3.2.2, Table 3.5.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.