x86-64.net

APX

APX-EVEX-CMPCCXADD exception class

APX-EVEX-CMPCCXADD is the APX specification's exception class for CMPccXADD in its EVEX encoding, which APX adds so that the instruction can use the registers R16 to R31.

Class
APX-EVEX-CMPCCXADD in Intel XED
Applies to
The EVEX encodings of the 16 CMPccXADD instructions, from CMPBEXADD to CMPZXADD, in map 2 with the opcodes of their VEX forms.
Instructions
1 mnemonic, 2 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the EVEX prefix raises #UD in real-address and virtual-8086 mode.
#UDAlways: CMPccXADD exists only in 64-bit mode.
#UDXCR0 bit 19 (APX) or CR4.OSXSAVE is 0: the operating system has not enabled APX.
#UDA bit of the last EVEX payload byte other than V4 and L is 1, or EVEX.L is 1.
#UDThe destination is a register (ModRM.mod = 11B): it must be memory.
#UDAny other invalid-opcode condition of the VEX form holds.
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCPUID reports no APX_F or no CMPCCXADD.
#SS(0)The memory address uses the SS segment and is not canonical.
#GP(0)The memory address is not canonical.
#GP(0)The memory operand is not naturally aligned: to 4 bytes, or to 8 for the 64-bit form.
#PF(fault-code)The memory access causes a page fault.

Notes

The APX table lists a misaligned memory operand as #GP(0) and has no #AC row, while the SDM’s exception type 14 for the VEX form of CMPccXADD has an #AC(0) row and no alignment #GP. Like the other promoted instructions that use only general-purpose registers, the EVEX form ignores CR0.TS and never raises #NM.

  • avx-type-14: CMPccXADD, which compares a value in memory and adds to it in one atomic step, the class that Intel's manual calls Exceptions Type 14.
  • APX-EVEX-RAO-INT: APX-EVEX-RAO-INT is the APX specification's exception class for the remote atomic operations AADD, AAND, AOR and AXOR in their EVEX encoding, which APX adds so that they can use the registers R16 to R31.

Instructions

Intel XED puts forms of 1 mnemonic in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

APX

Sources

  1. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025): Section 4.2.9, Table 4.10; Section 3.1.2.3.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.6.2, Table 2-31.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.