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APX

APX-EVEX-ENQCMD exception class

APX-EVEX-ENQCMD is the APX specification's exception class for ENQCMD and ENQCMDS in their EVEX encoding, which send a 64-byte command to a device's enqueue register.

Class
APX-EVEX-ENQCMD in Intel XED
Applies to
The EVEX encodings of ENQCMD and ENQCMDS, in map 4.
Instructions
2 mnemonics, 2 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the EVEX prefix raises #UD in real-address and virtual-8086 mode.
#UDAlways: EVEX map 4, where these instructions are, exists only in 64-bit mode.
#UDXCR0 bit 19 (APX) or CR4.OSXSAVE is 0: the operating system has not enabled APX.
#UDA bit of the last EVEX payload byte other than V4 is 1, or EVEX.V4 and EVEX.vvvv are not all 1s.
#UDThe source is a register (ModRM.mod = 11B): it must be memory.
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCPUID reports no APX_F or no ENQCMD.
#SS(0)The memory address uses the SS segment and is not canonical.
#GP(0)The memory address is not canonical.
#GP(0)The destination address, taken from the register operand, is not 64-byte aligned.
#GP(0)Bits 30:20 of the 64-byte command read from the source are not zero.
#GP(0)ENQCMD only: bits 19:0 of the source are not zero; ENQCMD inserts the PASID itself.
#GP(0)ENQCMD only: IA32_PASID does not hold a valid PASID (its valid bit is 0).
#GP(0)ENQCMDS only: CPL is not 0.
#PF(fault-code)A memory access causes a page fault.

Notes

ENQCMD takes the process address space identifier (PASID) from IA32_PASID, which the operating system loads for each thread, and marks the command as a user’s. The supervisor version, ENQCMDS, passes the PASID and the privilege bit from its source instead. The APX table lists bits 30:20 and 19:0 of ENQCMD’s source; the SDM’s page for ENQCMD requires all of bits 31:0 to be zero.

  • APX-EVEX-INT: APX-EVEX-INT is the APX specification's exception class for the integer instructions that APX promotes from the legacy maps into EVEX map 4, for the registers R16 to R31, a new destination register (NDD), flag suppression (NF) and zero-upper forms (ZU).

Instructions

Intel XED puts forms of 2 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

APX

Sources

  1. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025): Section 4.2.10, Table 4.11.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): ENQCMD and ENQCMDS, Description and 64-Bit Mode Exceptions.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.