x86-64.net

APX

APX-EVEX-INT exception class

APX-EVEX-INT is the APX specification's exception class for the integer instructions that APX promotes from the legacy maps into EVEX map 4, for the registers R16 to R31, a new destination register (NDD), flag suppression (NF) and zero-upper forms (ZU).

Class
APX-EVEX-INT in Intel XED
Applies to
The EVEX map 4 encodings of ADC, ADCX, ADD, ADOX, AND, CMOVcc, CRC32, DEC, DIV, IDIV, IMUL, INC, LZCNT, MOVBE, MOVDIR64B, MOVDIRI, MUL, NEG, NOT, OR, POPCNT, RCL, RCR, ROL, ROR, SAR, SBB, SETcc, SHL, SHLD, SHR, SHRD, SUB, TZCNT and XOR.
Instructions
35 mnemonics, 617 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the EVEX prefix raises #UD in real-address and virtual-8086 mode.
#UDAlways: EVEX map 4, where these instructions are, exists only in 64-bit mode.
#UDXCR0 bit 19 (APX) or CR4.OSXSAVE is 0: the operating system has not enabled APX.
#UDA bit of the last EVEX payload byte other than ND, V4 and NF is 1.
#UDEVEX.ND is 1 on an instruction without an NDD or ZU form, or EVEX.NF is 1 on one without an NF form.
#UDEVEX.V4 and EVEX.vvvv are not all 1s although they name no register: EVEX.ND is 0, or the instruction uses ND for ZU (SETcc and IMUL with an immediate).
#UDThe operand is a register (ModRM.mod = 11B) and EVEX.U is 0.
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCPUID reports no APX_F, or not the feature that ADCX, ADOX, CRC32, MOVBE, POPCNT, MOVDIR64B or MOVDIRI also requires.
#SS(0)The memory address uses the SS segment and is not canonical.
#GP(0)The memory address is not canonical.
#GP(0)MOVDIR64B only: the destination address in the register operand is not 64-byte aligned.
#PF(fault-code)The memory access causes a page fault.
#AC(0)Alignment checking is enabled, CPL is 3 and the memory access is unaligned.
#DEDIV and IDIV only: the divisor is 0, or the quotient does not fit the destination.

Notes

Which instruction allows which bit:

  • ND for a new destination (NDD), the register in EVEX.vvvv: INC, DEC, NOT, NEG, ADD, SUB, ADC, SBB, AND, OR, XOR, the shifts and rotates, SHLD, SHRD, ADCX, ADOX, CMOVcc and the two-operand IMUL.
  • ND for zero-upper (ZU), which clears bits 63:8 or 63:16 of an 8- or 16-bit register destination: SETcc and IMUL with an immediate.
  • NF, no flags update: INC, DEC, NEG, ADD, SUB, AND, OR, XOR, the shifts and rotates other than RCL and RCR, SHLD, SHRD, IMUL, MUL, DIV, IDIV, LZCNT, TZCNT and POPCNT.

The class has no #NM: promoted instructions that use only general-purpose registers ignore CR0.TS. See ADD for the forms of a typical member.

  • APX-EVEX-BMI: APX-EVEX-BMI is the APX specification's exception class for the BMI1 and BMI2 instructions in their EVEX encoding, which APX adds so that they can use the registers R16 to R31 and, for some of them, leave the flags unchanged.
  • APX-EVEX-CFCMOV: APX-EVEX-CFCMOV is the APX specification's exception class for CFCMOVcc, the conditionally faulting CMOVcc of EVEX map 4, whose memory faults and debug exceptions occur only when the condition is true.

Instructions

Intel XED puts forms of 35 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

APX

Sources

  1. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025): Section 4.2.11, Table 4.12; Sections 3.1.2.3 and 3.1.2.3.1.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.