x86-64.net

APX

APX-EVEX-INVVPID exception class

APX-EVEX-INVVPID is the APX specification's exception class for INVVPID in its EVEX encoding, the VMX instruction that invalidates translations by virtual-processor identifier (VPID).

Class
APX-EVEX-INVVPID in Intel XED
Applies to
The EVEX encoding of INVVPID (VMX), in map 4.
Instructions
1 mnemonic, 1 form
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the EVEX prefix raises #UD in real-address and virtual-8086 mode.
#UDAlways: EVEX map 4, where this instruction is, exists only in 64-bit mode.
#UDXCR0 bit 19 (APX) or CR4.OSXSAVE is 0: the operating system has not enabled APX.
#UDA bit of the last EVEX payload byte other than V4 is 1, or EVEX.V4 and EVEX.vvvv are not all 1s.
#UDThe descriptor operand is a register (ModRM.mod = 11B): it must be memory.
#UDThe processor is not in VMX operation, or it does not support VPIDs or the INVVPID instruction.
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCPUID reports no APX_F, or not a feature the instruction also needs.
#SS(0)The memory address uses the SS segment and is not canonical.
#GP(0)The memory address is not canonical.
#GP(0)CPL is not 0.
#PF(fault-code)Reading the descriptor causes a page fault.

Notes

As with INVEPT, the table lists only exceptions. In VMX non-root operation INVVPID causes a VM exit, and an invalid type or descriptor ends in VMfail, reported in the flags.

  • APX-EVEX-INVEPT: APX-EVEX-INVEPT is the APX specification's exception class for INVEPT in its EVEX encoding, the VMX instruction that invalidates translations derived from extended page tables (EPT).
  • APX-EVEX-INVPCID: APX-EVEX-INVPCID is the APX specification's exception class for INVPCID in its EVEX encoding, which invalidates TLB entries by process-context identifier (PCID).

Instructions

Intel XED puts forms of 1 mnemonic in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

APX

Sources

  1. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025): Section 4.2.14, Table 4.15.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026): Section 33.3, INVVPID, Operation.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.