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APX

APX-EVEX-KMOV exception class

APX-EVEX-KMOV is the APX specification's exception class for KMOVB, KMOVW, KMOVD and KMOVQ in their EVEX encoding, which APX adds so that the moves between mask registers and general-purpose registers or memory can use R16 to R31.

Class
APX-EVEX-KMOV in Intel XED
Applies to
The EVEX encodings of KMOVB, KMOVW, KMOVD and KMOVQ, in map 1 with the opcodes of their VEX forms.
Instructions
4 mnemonics, 20 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the EVEX prefix raises #UD in real-address and virtual-8086 mode.
#UDAlways: the EVEX forms of KMOV exist only in 64-bit mode.
#UDXCR0 bit 19 (APX) or CR4.OSXSAVE is 0: the operating system has not enabled APX.
#UDA bit of the last EVEX payload byte other than V4 and L is 1, EVEX.L is 1, or EVEX.V4 and EVEX.vvvv are not all 1s.
#UDThe operand is a register (ModRM.mod = 11B) and EVEX.U is 0.
#UDAny other invalid-opcode condition of the VEX form holds.
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCPUID reports no APX_F, or neither AVX10.1 nor the AVX-512 subset of the operand size: AVX512F for KMOVW, AVX512DQ for KMOVB, AVX512BW for KMOVD and KMOVQ.
#NMCR0.TS is 1.
#SS(0)The memory address uses the SS segment and is not canonical.
#GP(0)The memory address is not canonical.
#PF(fault-code)The memory access causes a page fault.
#AC(0)Alignment checking is enabled, CPL is 3 and the memory access is unaligned.

Notes

Unlike the other promoted VEX instructions, the KMOV forms keep the #NM for CR0.TS, since they use the mask registers of AVX-512. For the remaining #UD conditions, the APX table points to Tables 2-37 and 2-39 of SDM Volume 2. In revision 093 of the SDM, the VEX forms of the mask instructions have exception types K20 and K21 (Section 2.9), which among other things require XCR0 to enable the AVX-512 state (Table 2-39).

  • AVX512-K20: VEX-encoded instructions on opmask registers without a memory operand, such as KANDW, KORTESTQ and KSHIFTLD, which Intel's manual calls Exceptions Type K20.
  • AVX512-K21: The VEX-encoded opmask moves KMOVB, KMOVW, KMOVD and KMOVQ in the forms that can address memory, which Intel's manual calls Exceptions Type K21.

Instructions

Intel XED puts forms of 4 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

APX

Sources

  1. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025): Section 4.2.15, Table 4.16.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.9, Tables 2-65 and 2-66; Section 2.7.11.1, Table 2-39; KMOVW/KMOVB/KMOVQ/KMOVD, opcode table.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.