x86-64.net

APX

APX-EVEX-MOVRS exception class

APX-EVEX-MOVRS is the APX specification's exception class for MOVRS in its EVEX encoding, a load with a hint that other processors will read the same data.

Class
APX-EVEX-MOVRS in Intel XED
Applies to
The EVEX encodings of MOVRS (MOVRS), in map 4, whose registers can be R16 to R31.
Instructions
1 mnemonic, 2 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: MOVRS exists only in 64-bit mode.
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDEVEX.L is 1, or EVEX.V4 and EVEX.vvvv are not all 1s.
#UDA bit of the last EVEX payload byte other than V4 is 1.
#UDCPUID reports no MOVRS or no APX_F.
#UDXCR0 bit 19 (APX) or CR4.OSXSAVE is 0: the operating system has not enabled APX.
#SS(0)The memory address uses the SS segment and is not canonical.
#GP(0)The memory address is not canonical.
#PF(fault-code)The load causes a page fault.
#AC(0)Alignment checking is enabled, CPL is 3 and the load is unaligned.

Notes

Apart from the EVEX fields and the APX enabling, the class matches LEGACY-MOVRS of the legacy encoding: MOVRS faults like any other load.

  • LEGACY-MOVRS: LEGACY-MOVRS is the ISE's exception class Legacy-MOVRS of the MOVRS load in its legacy encoding: #UD outside 64-bit mode or with a LOCK or REP prefix, and the faults of an ordinary load.
  • LEGACY-PREFETCH: LEGACY-PREFETCH is XED's name for the exceptions of PREFETCHRST2, which the ISE lists on the instruction's page: #UD for a LOCK prefix, in every mode, and nothing else.

Instructions

Intel XED puts forms of 1 mnemonic in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

APX

Sources

  1. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025): Section 4.2.16, Table 4.17.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.