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APX

APX-EVEX-PP2 exception class

APX-EVEX-PP2 is the APX specification's exception class for PUSH2 and POP2, which push or pop two 64-bit registers at once, and for their forms with the balanced push-pop hint.

Class
APX-EVEX-PP2 in Intel XED
Applies to
PUSH2, POP2 and the hinted PUSH2P and POP2P (APX), in EVEX map 4.
Instructions
4 mnemonics, 4 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the EVEX prefix raises #UD in real-address and virtual-8086 mode.
#UDAlways: EVEX map 4, where these instructions are, exists only in 64-bit mode.
#UDXCR0 bit 19 (APX) or CR4.OSXSAVE is 0: the operating system has not enabled APX.
#UDA bit of the last EVEX payload byte other than ND and V4 is 1, or EVEX.ND is 0: ND must be 1, as EVEX.vvvv names the second register.
#UDModRM.mod is not 11B or EVEX.U is 0: both operands must be registers.
#UDEither register is RSP, or a POP2 names the same register twice.
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCPUID reports no APX_F.
#SS(0)The stack address, in the SS segment, is not canonical.
#GP(0)The memory address is not canonical.
#GP(0)RSP is not 16-byte aligned, so the two 8-byte slots would not form one aligned 16-byte block.
#PF(fault-code)The stack access causes a page fault.

Notes

PUSH2 and POP2 need RSP aligned to 16 bytes. PUSH2P and POP2P set EVEX.W to mark a push and its matching pop for the processor’s push-pop acceleration (PPX); the hint changes neither the result nor the exceptions.

  • APX-EVEX-INT: APX-EVEX-INT is the APX specification's exception class for the integer instructions that APX promotes from the legacy maps into EVEX map 4, for the registers R16 to R31, a new destination register (NDD), flag suppression (NF) and zero-upper forms (ZU).

Instructions

Intel XED puts forms of 4 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

APX

Sources

  1. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025): Section 4.2.17, Table 4.18; Sections 3.1.3.1.1 and 3.1.3.1.2.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.