x86-64.net

APX

APX-EVEX-RAO-INT exception class

APX-EVEX-RAO-INT is the APX specification's exception class for the remote atomic operations AADD, AAND, AOR and AXOR in their EVEX encoding, which APX adds so that they can use the registers R16 to R31.

Class
APX-EVEX-RAO-INT in Intel XED
Applies to
The EVEX encodings of AADD, AAND, AOR and AXOR (RAO-INT), in map 4.
Instructions
4 mnemonics, 8 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the EVEX prefix raises #UD in real-address and virtual-8086 mode.
#UDAlways: EVEX map 4, where these instructions are, exists only in 64-bit mode.
#UDXCR0 bit 19 (APX) or CR4.OSXSAVE is 0: the operating system has not enabled APX.
#UDA bit of the last EVEX payload byte other than V4 is 1, or EVEX.V4 and EVEX.vvvv are not all 1s.
#UDThe destination is a register (ModRM.mod = 11B): it must be memory.
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDCPUID reports no APX_F or no RAO-INT.
#SS(0)The memory address uses the SS segment and is not canonical.
#GP(0)The memory address is not canonical.
#GP(0)The destination is not naturally aligned: to 4 bytes, or to 8 for the 64-bit form.
#GP(0)The destination’s memory type is not write-back (WB).
#PF(fault-code)The memory access causes a page fault.

Notes

Remote atomic operations may be carried out close to memory, in a shared cache or the memory controller. They require natural alignment so that one update never straddles two cache lines, and a misaligned destination, like one whose memory type is not write-back, raises #GP(0) rather than #AC. The legacy encoding of AADD and its siblings has LEGACY-RAO-INT.

  • LEGACY-RAO-INT: LEGACY-RAO-INT is XED's name for the exceptions of the remote atomic operations AADD, AAND, AOR and AXOR in their legacy encoding, which the ISE lists on the instruction pages rather than as a named class.
  • APX-EVEX-CMPCCXADD: APX-EVEX-CMPCCXADD is the APX specification's exception class for CMPccXADD in its EVEX encoding, which APX adds so that the instruction can use the registers R16 to R31.

Instructions

Intel XED puts forms of 4 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

APX

Sources

  1. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025): Section 4.2.18, Table 4.19.
  2. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026): Sections 5.1 and 5.3.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.