AVX
avx-type-11 exception class
The F16C conversions VCVTPH2PS and VCVTPS2PH between half and single precision, which Intel's manual calls Exceptions Type 11.
- Class
avx-type-11in Intel XED- Applies to
- The VEX encodings of VCVTPH2PS and VCVTPS2PH.
- Instructions
- 2 mnemonics, 8 forms
- Data
- Intel XED v2026.08.23
Exception conditions
| Exception | Real | Virtual-8086 | Protected | 64-bit | Condition |
|---|---|---|---|---|---|
#UD | yes | yes | no | no | Always: real and virtual-8086 mode have no VEX prefix. |
#UD | no | no | yes | yes | The operating system has not enabled the AVX state: CR4.OSXSAVE is 0, or XCR0 bits 1 and 2 (SSE and AVX state) are not both 1. |
#UD | yes | yes | yes | yes | The instruction has a LOCK prefix (F0). |
#UD | no | no | yes | yes | A REX, F2, F3 or 66 prefix comes before the VEX prefix. |
#UD | yes | yes | yes | yes | The processor lacks the instruction’s extension: its CPUID feature flag is 0. |
#UD | no | no | yes | yes | VEX.W is 1, or VEX.vvvv is not 1111b. |
#NM | yes | yes | yes | yes | CR0.TS (task switched, bit 3) is 1. |
#SS(0) | no | no | yes | no | A memory operand addressed through SS lies outside the stack segment. |
#SS(0) | no | no | no | yes | A memory operand addressed through SS has a non-canonical address. |
#GP(0) | no | no | yes | no | A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit. |
#GP(0) | no | no | no | yes | A memory operand has a non-canonical address. |
#GP(0) | yes | yes | no | no | A memory operand extends past offset FFFFh of its segment. |
#PF(fault-code) | no | yes | yes | yes | Accessing a memory operand causes a page fault. |
#XM | yes | yes | yes | yes | A SIMD floating-point exception that MXCSR does not mask occurs, and CR4.OSXMMEXCPT is 1. |
Notes
The class has #XM but no #AC: the manual’s page for VCVTPS2PH says
that these conversions do not report #AC, whatever the alignment.
The #UD for VEX.W = 1 comes from Table 2-16, the one for
VEX.vvvv from the page of VCVTPS2PH.
Related classes
Instructions
Intel XED puts forms of 2 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.
F16C
Sources
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5.9, Table 2-26; Section 2.5, Tables 2-14 to 2-16; Chapter 5, VCVTPS2PH.
- Intel XED v2026.08.23 (commit
0bcb6237345c): the exception class of each instruction form.
The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.