AVX
avx-type-2 exception class
VEX-encoded floating-point arithmetic on full vectors, such as VADDPS, VSQRTPD and the FMA instructions, which Intel's manual calls Exceptions Type 2.
- Class
avx-type-2in Intel XED- Applies to
- VEX encodings, 128 and 256 bits, including those of FMA.
- Instructions
- 66 mnemonics, 264 forms
- Data
- Intel XED v2026.08.23
Exception conditions
| Exception | Real | Virtual-8086 | Protected | 64-bit | Condition |
|---|---|---|---|---|---|
#UD | yes | yes | no | no | Always: real and virtual-8086 mode have no VEX prefix. |
#UD | yes | yes | yes | yes | A SIMD floating-point exception that MXCSR does not mask occurs while CR4.OSXMMEXCPT is 0, the setting for an operating system that does not handle #XM. |
#UD | no | no | yes | yes | The operating system has not enabled the AVX state: CR4.OSXSAVE is 0, or XCR0 bits 1 and 2 (SSE and AVX state) are not both 1. |
#UD | yes | yes | yes | yes | The instruction has a LOCK prefix (F0). |
#UD | no | no | yes | yes | A REX, F2, F3 or 66 prefix comes before the VEX prefix. |
#UD | yes | yes | yes | yes | The processor lacks the instruction’s extension: its CPUID feature flag is 0. |
#NM | yes | yes | yes | yes | CR0.TS (task switched, bit 3) is 1. |
#SS(0) | no | no | yes | no | A memory operand addressed through SS lies outside the stack segment. |
#SS(0) | no | no | no | yes | A memory operand addressed through SS has a non-canonical address. |
#GP(0) | no | no | yes | no | A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit. |
#GP(0) | no | no | no | yes | A memory operand has a non-canonical address. |
#GP(0) | yes | yes | no | no | A memory operand extends past offset FFFFh of its segment. |
#PF(fault-code) | no | yes | yes | yes | Accessing a memory operand causes a page fault. |
#XM | yes | yes | yes | yes | A SIMD floating-point exception that MXCSR does not mask occurs, and CR4.OSXMMEXCPT is 1. |
Notes
Unlike the legacy forms (SSE_TYPE_2), the VEX forms accept a memory operand at any alignment: the manual’s table requires 16-byte alignment of the legacy encoding only.
A SIMD floating-point exception that MXCSR does not mask raises
#XM, or #UD while CR4.OSXMMEXCPT is 0.
Related classes
Instructions
Intel XED puts forms of 66 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.
AVX
- VADDPD
- VADDPS
- VADDSUBPD
- VADDSUBPS
- VCMPPD
- VCMPPS
- VCVTDQ2PS
- VCVTPD2DQ
- VCVTPD2PS
- VCVTPS2DQ
- VCVTTPD2DQ
- VCVTTPS2DQ
- VDIVPD
- VDIVPS
- VHADDPD
- VHADDPS
- VHSUBPD
- VHSUBPS
- VMAXPD
- VMAXPS
- VMINPD
- VMINPS
- VMULPD
- VMULPS
- VROUNDPD
- VROUNDPS
- VSQRTPD
- VSQRTPS
- VSUBPD
- VSUBPS
FMA
- VFMADD132PD
- VFMADD132PS
- VFMADD213PD
- VFMADD213PS
- VFMADD231PD
- VFMADD231PS
- VFMADDSUB132PD
- VFMADDSUB132PS
- VFMADDSUB213PD
- VFMADDSUB213PS
- VFMADDSUB231PD
- VFMADDSUB231PS
- VFMSUB132PD
- VFMSUB132PS
- VFMSUB213PD
- VFMSUB213PS
- VFMSUB231PD
- VFMSUB231PS
- VFMSUBADD132PD
- VFMSUBADD132PS
- VFMSUBADD213PD
- VFMSUBADD213PS
- VFMSUBADD231PD
- VFMSUBADD231PS
- VFNMADD132PD
- VFNMADD132PS
- VFNMADD213PD
- VFNMADD213PS
- VFNMADD231PD
- VFNMADD231PS
- VFNMSUB132PD
- VFNMSUB132PS
- VFNMSUB213PD
- VFNMSUB213PS
- VFNMSUB231PD
- VFNMSUB231PS
Sources
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5.2, Table 2-19; Section 2.5, Tables 2-14 and 2-15.
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026): Section 11.5.1.
- Intel XED v2026.08.23 (commit
0bcb6237345c): the exception class of each instruction form.
The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.