Class
avx-type-2 in Intel XED
Applies to
VEX encodings, 128 and 256 bits, including those of FMA.
Instructions
66 mnemonics, 264 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDyesyesnonoAlways: real and virtual-8086 mode have no VEX prefix.
#UDyesyesyesyesA SIMD floating-point exception that MXCSR does not mask occurs while CR4.OSXMMEXCPT is 0, the setting for an operating system that does not handle #XM.
#UDnonoyesyesThe operating system has not enabled the AVX state: CR4.OSXSAVE is 0, or XCR0 bits 1 and 2 (SSE and AVX state) are not both 1.
#UDyesyesyesyesThe instruction has a LOCK prefix (F0).
#UDnonoyesyesA REX, F2, F3 or 66 prefix comes before the VEX prefix.
#UDyesyesyesyesThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#NMyesyesyesyesCR0.TS (task switched, bit 3) is 1.
#SS(0)nonoyesnoA memory operand addressed through SS lies outside the stack segment.
#SS(0)nononoyesA memory operand addressed through SS has a non-canonical address.
#GP(0)nonoyesnoA memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
#GP(0)nononoyesA memory operand has a non-canonical address.
#GP(0)yesyesnonoA memory operand extends past offset FFFFh of its segment.
#PF(fault-code)noyesyesyesAccessing a memory operand causes a page fault.
#XMyesyesyesyesA SIMD floating-point exception that MXCSR does not mask occurs, and CR4.OSXMMEXCPT is 1.

Notes

Unlike the legacy forms (SSE_TYPE_2), the VEX forms accept a memory operand at any alignment: the manual’s table requires 16-byte alignment of the legacy encoding only.

A SIMD floating-point exception that MXCSR does not mask raises #XM, or #UD while CR4.OSXMMEXCPT is 0.

Instructions

Intel XED puts forms of 66 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AVX

FMA

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5.2, Table 2-19; Section 2.5, Tables 2-14 and 2-15.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026): Section 11.5.1.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.