Class
avx-type-2D in Intel XED
Applies to
VEX encodings of VDPPD, which has only a 128-bit form, and VDPPS.
Instructions
2 mnemonics, 6 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDyesyesnonoAlways: real and virtual-8086 mode have no VEX prefix.
#UDyesyesyesyesA SIMD floating-point exception that MXCSR does not mask occurs while CR4.OSXMMEXCPT is 0, the setting for an operating system that does not handle #XM.
#UDnonoyesyesThe operating system has not enabled the AVX state: CR4.OSXSAVE is 0, or XCR0 bits 1 and 2 (SSE and AVX state) are not both 1.
#UDyesyesyesyesThe instruction has a LOCK prefix (F0).
#UDnonoyesyesA REX, F2, F3 or 66 prefix comes before the VEX prefix.
#UDyesyesyesyesThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#UDnonoyesyesVDPPD is encoded with VEX.L = 1: it has no 256-bit form.
#NMyesyesyesyesCR0.TS (task switched, bit 3) is 1.
#SS(0)nonoyesnoA memory operand addressed through SS lies outside the stack segment.
#SS(0)nononoyesA memory operand addressed through SS has a non-canonical address.
#GP(0)nonoyesnoA memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
#GP(0)nononoyesA memory operand has a non-canonical address.
#GP(0)yesyesnonoA memory operand extends past offset FFFFh of its segment.
#PF(fault-code)noyesyesyesAccessing a memory operand causes a page fault.
#XMyesyesyesyesA SIMD floating-point exception that MXCSR does not mask occurs, and CR4.OSXMMEXCPT is 1.

Notes

XED gives the dot products a class of their own. The manual’s pages for DPPD and DPPS refer them to the Type 2 table and add #UD for VDPPD with VEX.L = 1, which Table 2-17 lists as well, whether or not the processor has AVX2.

As for the legacy forms (SSE_TYPE_2D), each multiplication and addition of the dot product is checked for floating-point exceptions in turn.

Instructions

Intel XED puts forms of 2 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AVX

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5.2, Table 2-19; Section 2.5, Tables 2-15 and 2-17; Chapter 3, DPPD and DPPS.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.