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AVX

avx-type-3 exception class

VEX-encoded floating-point arithmetic on scalars and other operands smaller than 16 bytes, such as VADDSS, VCOMISD and the scalar FMA instructions, which Intel's manual calls Exceptions Type 3.

Class
avx-type-3 in Intel XED
Applies to
VEX encodings, including those of FMA.
Instructions
55 mnemonics, 124 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: real and virtual-8086 mode have no VEX prefix.
#UDA SIMD floating-point exception that MXCSR does not mask occurs while CR4.OSXMMEXCPT is 0, the setting for an operating system that does not handle #XM.
#UDThe operating system has not enabled the AVX state: CR4.OSXSAVE is 0, or XCR0 bits 1 and 2 (SSE and AVX state) are not both 1.
#UDThe instruction has a LOCK prefix (F0).
#UDA REX, F2, F3 or 66 prefix comes before the VEX prefix.
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#NMCR0.TS (task switched, bit 3) is 1.
#SS(0)A memory operand addressed through SS lies outside the stack segment.
#SS(0)A memory operand addressed through SS has a non-canonical address.
#GP(0)A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
#GP(0)A memory operand has a non-canonical address.
#GP(0)A memory operand extends past offset FFFFh of its segment.
#PF(fault-code)Accessing a memory operand causes a page fault.
#AC(0)Code at privilege level 3 makes a misaligned 2-, 4- or 8-byte memory access while alignment checking is on.
#XMA SIMD floating-point exception that MXCSR does not mask occurs, and CR4.OSXMMEXCPT is 1.

Notes

There is no alignment rule for #GP; a misaligned memory operand raises #AC(0) only when alignment checking is on at privilege level 3.

As in SSE_TYPE_3, the manual’s page for MINSS refers VMINSS to the Type 2 table, while Table 2-15 and XED put it here. The page of CVTSI2SD refers the VEX forms that convert a 32-bit integer to the Type 5 table; XED keeps both operand sizes of VCVTSI2SD here.

  • SSE_TYPE_3: Legacy SSE floating-point arithmetic on scalars and other operands smaller than 16 bytes, such as ADDSS, COMISD and CVTSI2SD, which Intel's manual calls Exceptions Type 3.
  • avx-type-2: VEX-encoded floating-point arithmetic on full vectors, such as VADDPS, VSQRTPD and the FMA instructions, which Intel's manual calls Exceptions Type 2.
  • avx-type-5: VEX-encoded moves, inserts, extracts and conversions on operands smaller than 16 bytes without floating-point exceptions, such as VMOVD, VPINSRB and VPMOVZXBW, which Intel's manual calls Exceptions Type 5.
  • AVX512-E3: EVEX-encoded floating-point arithmetic on scalars, such as VADDSS, VFMADD231SD and VCMPSD, with memory fault suppression, which Intel's manual calls Exceptions Type E3.

Instructions

Intel XED puts forms of 55 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AVX

FMA

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5.3, Table 2-20; Section 2.5, Tables 2-14 and 2-15; Chapter 3, CVTSI2SD; Chapter 4, MINSS.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.